Title: A novel high-performance and reliable multi-threshold CNFET full adder cell design

Authors: Yavar Safaei Mehrabani; Mohammad Hossein Shafiabadi

Addresses: Department of Computer Engineering, Varamin-Pishva Branch, Islamic Azad University, Tehran, Iran ' Department of Computer Engineering, IslamShahr Branch, Islamic Azad University, IslamShahr, Tehran, Iran

Abstract: Full adder cell is widely employed in larger circuits such as multiplier, compressor, address calculation of cache memory, and so on. Therefore, it plays an important role in determining the entire performance of digital system. In this paper, a novel high-speed, high-performance, and reliable full adder cell based on NAND, MAJORITY-not, and NOR at nanoscale using carbon nanotube field effect transistors (CNFETs) is presented. Several simulations have been carried out using different power supplies, load capacitors, frequencies, and temperatures at 32 nm-CMOS and 32 nm-CNFET technologies using HSPICE simulator tool. Simulation results demonstrate the superiority of the proposed cell in terms of delay and power-delay product (PDP) compared to other full adder cells. In addition, to evaluate the robustness of the CNFET-based full adder cells with respect to process variation (diameter mismatches of the CNFETs' nanotubes), Monte Carlo transient analysis is conducted. Experimental results confirm that the proposed design can function more properly and experience less diameter variations in the presence of the process fluctuations than the other cells do.

Keywords: carbon nanotube field effect transistor; CNFET; full adder cell; high-performance; nanoelectronics; process fluctuation.

DOI: 10.1504/IJHPSA.2017.083644

International Journal of High Performance Systems Architecture, 2017 Vol.7 No.1, pp.15 - 25

Received: 15 Feb 2016
Accepted: 25 Oct 2016
Published online: 13 Apr 2017 *

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