Int. J. of Wireless and Mobile Computing   »   2017 Vol.12, No.1

 

 

Title: Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA

 

Authors: Khalid Al-Hussaini; Borhanuddin M. Ali; Pooria Varahram; Shaiful J. Hashim; Ronan Farrell

 

Addresses:
Department of Computer and Communications Systems Engineering, Research Centre of Excellence for Wireless and Photonic Networks (WiPNET), Universiti Putra Malaysia, 43400 UPM Serdang, Selangor, Malaysia
Department of Computer and Communications Systems Engineering, Research Centre of Excellence for Wireless and Photonic Networks (WiPNET), Universiti Putra Malaysia, 43400 UPM Serdang, Selangor, Malaysia
Department of Electronic Engineering, National University of Ireland, Kildare, Ireland
Department of Computer and Communications Systems Engineering, Research Centre of Excellence for Wireless and Photonic Networks (WiPNET), Universiti Putra Malaysia, 43400 UPM Serdang, Selangor, Malaysia
Department of Electronic Engineering, CTVR - The Telecommunication Research Centre, Callan Institute, National University of Ireland, Kildare, Ireland

 

Abstract: This paper presents a novel low-complexity technique for reducing the Peak-to-Average Power Ratio (PAPR) in Orthogonal Frequency Division Multiplexing (OFDM) systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on a Field Programmable Gate Array (FPGA). In this technique, each subblock is interleaved with the others, and a new optimisation scheme is introduced in which the number of iterations is equal only to the number of subblocks, which results in reduced processing time and less computation that, in turn, leads to reduced complexity. Furthermore, the proposed method focuses on simplifying the required hardware resources. Thus, it can be easily combined with other simplified techniques. The simulation results demonstrate that the new technique can effectively reduce the complexity up to 98.22% compared with the new existing Partial Transmit Sequence (PTS) techniques and yield a good Bit Error Rate (BER) performance. Through the comparison of performance between simulation and hardware, it is distinctly illustrated that the designed hardware block diagram is as workable as the simulation and the difference of the result is only 0.1 dB.

 

Keywords: OFDM; hardware co-simulation; FPGA; PAPR reduction; peak-to-average power ratio; orthogonal frequency division multiplexing; field programmable gate arrays; optimisation; simulation; partial transmit sequence; PTS; bit error rate; BER.

 

DOI: 10.1504/IJWMC.2017.10003984

 

Int. J. of Wireless and Mobile Computing, 2017 Vol.12, No.1, pp.49 - 61

 

Submission date: 02 May 2016
Date of acceptance: 08 Dec 2016
Available online: 18 Mar 2017

 

 

Editors Full text accessAccess for SubscribersPurchase this articleComment on this article