Title: FPGA implementation of multiphase DPWM generator with phase shedding for DC-DC converters

Authors: Michael Carswell III; Jaber Abu Qahouq

Addresses: Department of Electrical and Computer Engineering, University of Alabama, Tuscaloosa, AL 35487, USA ' Department of Electrical and Computer Engineering, University of Alabama, Tuscaloosa, AL 35487, USA

Abstract: The advantages of digital control in power electronics have led to an increasing use of digital pulse width modulators (DPWM). A major focus has been on optimising the DPWM signals and architecture for DC-DC converters to maximise power conversion efficiency and reduce the overall footprint. This paper presents and discusses a dual edge counter-comparator based multiphase DPWM generator with phase-shedding and current sharing functionalities. Phase shedding, or phase dropping, in multiphase power converter is a method that uses turning OFF some of the power converter phases/channels as the load current becomes smaller/lighter in order to improve the lighter load efficiencies. The presented architecture is validated through simulated and experimental test results based off a FPGA implementation of the DPWM generator.

Keywords: FPGA implementation; field-programmable gate arrays; multiphase DPWM generators; DC-DC converters; digital circuits; digital control; digital PWM; pulse width modulation; interleave; inverters; phase dropping; phase shedding; power converters; power electronics; simulation.

DOI: 10.1504/IJPELEC.2015.075426

International Journal of Power Electronics, 2015 Vol.7 No.3/4, pp.185 - 206

Received: 23 Jul 2014
Accepted: 01 Aug 2015
Published online: 22 Mar 2016 *

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