Title: XEMU: a cross-ISA full-system emulator on multiple processor architectures

Authors: Huang Wang; Chao Wang; Huaping Chen

Addresses: School of Computer Science, University of Science and Technology of China, No. 443, Huangshan Road, Hefei, Anhui, China ' School of Computer Science, University of Science and Technology of China, No. 188, Ren'ai Road, Suzhou, Jiangsu, China ' School of Computer Science, University of Science and Technology of China, No. 443, Huangshan Road, Hefei, Anhui, China

Abstract: Cross-instruction set architecture (ISA) full-system emulator plays an important role in reusing binary codes across different architectures. With the rapid development of multi-core technology, it is desirable to build a high-performance multi-core emulator rather than conventional single core emulator. However, current mainstream cross-ISA full-system emulator can only work sequentially, which seriously confines the parallelism. In order to take the advantage of parallelism of host platform to emulate multi processor architecture, this paper presents XE-MU, a cross-ISA full-system emulator on multiple processor architectures. Firstly, efficient methods are targeted to translate atomic instructions. Secondly, we study the approach to emulation of communications for inter-core and core-to-I/O devices. For the implementation, we utilise both GCC built-in-functions and LL/SC instructions-based methods to translate the atomic instructions. We propose a portable and efficient lock-free queue implementation for communications in virtual machine. In order to verify the effectiveness of these methods, we conducted experiments on the Loongson-3A hardware platform. Experimental results demonstrate that both methods are able to enhance the performance of the emulator and reduce the overhead of inter-core communication with interrupts; thereby, the efficiency of the emulator can be greatly improved.

Keywords: virtual machines; dynamic binary translation; lock free buffer; full-system emulators; cross-ISA; instruction set architecture; multiprocessor architectures; binary codes; binary code reuse; inter-core communication; interrupts.

DOI: 10.1504/IJHPSA.2015.072853

International Journal of High Performance Systems Architecture, 2015 Vol.5 No.4, pp.228 - 239

Received: 15 May 2015
Accepted: 08 Jul 2015
Published online: 04 Nov 2015 *

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