Title: High-performance ternary logic gates for nanoelectronics

Authors: Mohammad Hossein Moaiyeri; Mohsen Shamohammadi; Fazel Sharifi; Keivan Navi

Addresses: Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Velenjak, 1983963113, Tehran, Iran ' Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, G.C., Velenjak, 1983963113, Tehran, Iran ' Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Velenjak, 1983963113, Tehran, Iran ' Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Velenjak, 1983963113, Tehran, Iran

Abstract: This paper presents high-performance ternary buffer (STB), minimum (STMin) and maximum (STMax) circuits using carbon nanotube field effect transistors (CNTFETs). Multiple valued logic (MVL) has been introduced to overcome the complexity and interconnection problems of the binary integrated circuits. In addition, outstanding properties of CNTFETs such as possibility of adopting the desired threshold voltage make them very appropriate for voltage mode MVL circuits design. All circuits are examined in different conditions using Synopsys HSPICE simulator at 32 nm feature size. Power-delay product (PDP) of the proposed designs are lower than the latest presented ternary circuits about 33%, 33% and 64%, respectively.

Keywords: nanoelectronics; multiple valued logic; MVL circuit design; CNTFET; ternary logic gates; nanotechnology; carbon nanotubes; CNTs; CNT field effect transistors; FETs; nanotechnology.

DOI: 10.1504/IJHPSA.2015.072850

International Journal of High Performance Systems Architecture, 2015 Vol.5 No.4, pp.209 - 215

Received: 14 Apr 2015
Accepted: 15 Jun 2015
Published online: 04 Nov 2015 *

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