Title: A low-power voltage level converter for energy-efficient nanoelectronic circuits

Authors: Mohammad Hossein Moaiyeri; Behzad Alidoosti; Majid Moghaddam

Addresses: Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Velenjak, 1983963113, Tehran, Iran ' Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, G.C., Velenjak, 1983963113, Tehran, Iran ' Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Velenjak, 1983963113, Tehran, Iran

Abstract: In this paper, a new single supply level converter (SSLC) and a low-power multiplier based on CNTFET are proposed. Multi-V_th and staked CNTFETs are utilised suitably to reduce the power of the proposed LC which is able to convert ultra-low-voltage signals, to signals with more than 1 V amplitude. In addition, the proposed SSLC is utilised to design an energy-efficient double supply multiplier which benefits from clustered voltage scaling to reduce the number of required LCs. The results of the simulations, conducted using the Stanford comprehensive CNTFET SPICE model at 32 nm feature size, indicate the superiority of the proposed designs in terms of total power, static power, energy efficiency and sensitivity to process variations as compared with the other common LC circuits. The results show almost on average 30%, 68%, 97% and 73% improvements in terms of delay, total power, static power and energy consumption, respectively. In addition, utilising the proposed SSLC in the proposed multi-VDD multiplier leads to about 53%, 50% and 26% improvements in terms of total power, static power and energy consumption, respectively, as compared with the single-supply multiplier.

Keywords: nanoelectronics; carbon nanotubes; CNTs; CNT FETs; field-effect transistors; low-power design; voltage level converters; nanotechnology; circuit simulation; energy efficiency; double supply multipliers; clustered voltage scaling; total power; static power; process variations.

DOI: 10.1504/IJCAD.2015.072616

International Journal of Circuits and Architecture Design, 2015 Vol.1 No.4, pp.343 - 354

Received: 16 Feb 2015
Accepted: 22 Mar 2015
Published online: 22 Oct 2015 *

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