Title: Hardware implementation based on FPGA of semaphore management in μC/OS-II real-time operating system

Authors: Shi-hai Zhu

Addresses: College of Information Engineering and Art Design, Zhejiang University of Water Resources and Electric Power, Hangzhou 310018, China

Abstract: Semaphore is a kind of mechanism used in a multithreaded environment to ensure that two or more key code segments are not concurrently invoked. In order to enhance the response capability of real-time operating systems, a hardware design scheme to implement semaphore management based on field programmable gate array is put forward in this paper. We take the μC/OS-II real-time operating system as an example to design hardware logical circuits of semaphore management function module according to its parallel characteristics, and simulation tests under Xilinx ISE software environment are performed. The simulation results show that implementing semaphore management by hardware can obviously improve the execution time of creating/deleting a semaphore, applying for/releasing a semaphore and P/V operations; therefore, the whole reliability of the real-time operating system is greatly improved.

Keywords: semaphore management; event control block; system calls; field programmable gate arrays; software hardening; hardware design; FPGAs; real-time operating systems; simulation.

DOI: 10.1504/IJGUC.2015.070677

International Journal of Grid and Utility Computing, 2015 Vol.6 No.3/4, pp.192 - 199

Received: 05 Jul 2014
Accepted: 08 Aug 2014
Published online: 18 Jul 2015 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article