Article: A placer for composable FPGA with 2D mesh network Journal: International Journal of Embedded Systems (IJES) 2014 Vol.6 No.4 pp.289 - 302 Abstract: FPGAs are predominantly used for acceleration of computationally intensive algorithmic kernels. The ubiquitous co-processor abstraction, in which an application offloads such kernels to the FPGA, does not scale with current and future architectural advancements in FPGA technology. The rapid march of fabrication technology into the sub-micron era has resulted in packing of multiple blocks of programmable resources such as hard CPU cores, DSP modules, and fast multipliers on contemporary FPGA. Optimisation benefits from these advancements and the unique advantage of programmability have made FPGA an attractive alternative for complex system on chip (SoC) designs over other solutions. Adoption of the co-processor model in current generation of programmable architectures relegates the hard problem of hardware abstraction to the application and hence, the programmer. We propose a FPGA abstraction with native 2D-mesh network in order to improve the run time reconfigurability of multiple accelerators. In this paper, we describe a composable FPGA virtualisation framework to wean away the dependence of FPGA applications on the co-processor model. A novel run time placement algorithm, which minimises the communication energy between the accelerator modules, is evaluated on an embedded video application to demonstrate the placement efficiency in our framework. Inderscience Publishers - linking academia, business and industry through research

Title: A placer for composable FPGA with 2D mesh network

Authors: Ka-Ming Keung; Swamy D. Ponpandi; Akhilesh Tyagi

Addresses: Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, 50010, USA ' Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, 50010, USA ' Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, 50010, USA

Abstract: FPGAs are predominantly used for acceleration of computationally intensive algorithmic kernels. The ubiquitous co-processor abstraction, in which an application offloads such kernels to the FPGA, does not scale with current and future architectural advancements in FPGA technology. The rapid march of fabrication technology into the sub-micron era has resulted in packing of multiple blocks of programmable resources such as hard CPU cores, DSP modules, and fast multipliers on contemporary FPGA. Optimisation benefits from these advancements and the unique advantage of programmability have made FPGA an attractive alternative for complex system on chip (SoC) designs over other solutions. Adoption of the co-processor model in current generation of programmable architectures relegates the hard problem of hardware abstraction to the application and hence, the programmer. We propose a FPGA abstraction with native 2D-mesh network in order to improve the run time reconfigurability of multiple accelerators. In this paper, we describe a composable FPGA virtualisation framework to wean away the dependence of FPGA applications on the co-processor model. A novel run time placement algorithm, which minimises the communication energy between the accelerator modules, is evaluated on an embedded video application to demonstrate the placement efficiency in our framework.

Keywords: reconfiguration; field programmable gate arrays; FPGAs; CLB; configurable logic block; run time placement; embedded systems; placers; co-processor abstraction; virtualisation; on chip networks; 2D mesh networks; multiple accelerators.

DOI: 10.1504/IJES.2014.064986

International Journal of Embedded Systems, 2014 Vol.6 No.4, pp.289 - 302

Received: 08 Oct 2013
Accepted: 01 Dec 2013
Published online: 11 Oct 2014 *

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Title: A placer for composable FPGA with 2D mesh network

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