Title: An innovative model of multi-project wafer service in the foundry industry

Authors: Tai-Yih Yang, Lee-Ing Tong, Benjamin J.C. Yuan

Addresses: Department of Industrial Engineering and Management, National Chiao Tung University, 1001 Ta-Hsueh Rd., Hsinchu, Taiwan, ROC. ' Department of Industrial Engineering and Management, National Chiao Tung University, 1001 Ta-Hsueh Rd., Hsinchu, Taiwan, ROC. ' Institute of Management of Technology, National Chiao Tung University, 1001 Ta-Hsueh Rd., Hsinchu, Taiwan, ROC

Abstract: The cost of masks is rising rapidly as semiconductor manufacturing technology advances. This increase in cost is a major issue in the development of new products. This study focuses mainly on the business demands of semiconductor design companies who verify the prototypes and produce small-volume wafers, and analyses the constraints on the current Multi-Project Wafer (MPW) model. A new MPW model is proposed to reduce the mask cost and the unit die cost simultaneously. The proposed MPW model allows customers to find the optimal solution to the mask cost and unit die cost according to the chip size and the number of dice required. This study also compares the current model with the proposed MPW model using 0.13 µm technology, as an example. For a purchased quantity of dice from a few thousand to less than a hundred thousand, the proposed MPW model yields the lowest sum of the mask cost and the dice cost. Since this range of dice quantities covers more than half of the dice required for semiconductor products, the proposed MPW model can help the semiconductor industry to resolve the conflict between the mask cost and the unit die cost that is caused by the constraints on the current MPW model. When the technology advances to the 90 nm generation, and requested die quantities increased to more than 100,000, the small-volume MPW model proposed in this study will still yield the lowest mask cost and total dice cost.

Keywords: multi-project wafer model; prototyping verification; small-volume production; semiconductor manufacture; semiconductor design; mask cost; unit die cost; cost reduction; wafer fabrication; foundry.

DOI: 10.1504/IJTM.2005.006349

International Journal of Technology Management, 2005 Vol.30 No.1/2, pp.172 - 187

Published online: 23 Feb 2005 *

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