Title: Power gating architecture implementation inside clock period to reduce power

Authors: Debanjali Nath; Priyanka Choudhury; Abhishek Nag; Sambhu Nath Pradhan

Addresses: Department of Electronics and communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India ' Department of Electronics and communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India ' Department of Electronics and communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India ' Department of Electronics and communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India

Abstract: In today's nanometre regime of device dimension, leakage power has become comparable to dynamic power. Along with the other leakage reduction techniques, power gating is a technique which is used to reduce standby leakage and dynamic power by shutting down the power supply of the inactive block of the circuit but the active blocks continues to dissipate power. It has been observed that there is a scope of using power gating in active block to reduce run time leakage. If the operating frequency is lower than the maximum operating frequency of the circuit, then within clock period there is a certain portion which is idle and in this period power gating may be applied. This paper concerns about the implementation of power gating in this idle time of the clock. Architecture of this power gating technique designed to work within the clock period termed as 'within-clock power gating' (WCPG) for minimising leakage and total power of the sequential circuits during active mode of operation has been proposed in this paper. In this architecture an ISCAS89 benchmark circuit has been implemented. Power results have been reported for different frequencies. Simulation of the implemented architecture in CADENCE VLSI tool at 45 nm technology shows up to 85% saving in leakage and around 10% saving in total power compared to the no power gating at 2.5 MHz frequency.

Keywords: within-clock power gating; power gating architecture; power reduction; standby leakage; isolation; run time leakage; simulation.

DOI: 10.1504/IJCAET.2014.063118

International Journal of Computer Aided Engineering and Technology, 2014 Vol.6 No.3, pp.310 - 323

Received: 18 Jan 2013
Accepted: 30 Apr 2013
Published online: 26 Jul 2014 *

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