Title: Development of LabVIEW-based multilevel inverter with reduced number of switches

Authors: A. Kirubakaran; D. Vijayakumar

Addresses: Department of Electrical Engineering, National Institute of Technology Warangal, Warangal 506 004, Andhra Pradesh, India ' School of Electrical Engineering, Vellore Institute of Technology, Vellore 632 014, Tamil Nadu, India

Abstract: In the present scenario, the development of multilevel inverter is becoming popular for industrial applications and higher scale renewable green power technologies such as fuel cell, PV cell and wind turbine systems connected to the load. But the traditional multilevel topologies have large components and complex Pulse Width Modulation (PWM) controller leading to reduced harmonics and voltage stress on the load. Therefore, a new topology of a cascaded multilevel inverter employing less number of switches with reduced gate driver circuits and simple control scheme is presented in this paper. A comprehensive MATLAB/Simulink model of a seven-level inverter and the generation of control pulses using multi-carrier-based PWM is evolved and discussed. With the aid of LabVIEW, an experimental prototype is developed and their results are compared with simulation results.

Keywords: multilevel inverters; H-bride inverters; carrier disposition; pulse width modulation; PWM techniques; total harmonic distortion; THD; simulation.

DOI: 10.1504/IJPELEC.2014.060709

International Journal of Power Electronics, 2014 Vol.6 No.1, pp.88 - 102

Received: 09 May 2013
Accepted: 29 Mar 2014
Published online: 23 Oct 2014 *

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