Title: Design and VLSI implementation of power efficient processor for object localisation in large WSN

Authors: Joyashree Bag; Rashmi Ranjan Sahoo; Pranab Kishore Dutta; Subir Kumar Sarkar

Addresses: Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata-700032, India ' Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata-700032, India ' Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata-700032, India ' Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata-700032, India

Abstract: The presence of multiple obstacles on the real deployed geographical area may hinder the effective operations of large scale wireless sensor network in terms of significant disturbance in proper routing, increased delay in data transmission and increased energy consumptions. To overcome this problem, a novel pulse mode object localisation algorithm and its VLSI implementation for designing the sensor node processor is proposed in this article. The algorithm supports distributed and energy efficient sleep scheduling with periodic synchronisation and reconfigure the routing scheme that can be used to extend the life time of sensor network. The algorithm is made power efficient by using pulse mode operation. It is a high performance sensor node processor with an overall power consumption of 0.012 mW in active mode with a dynamic current of 1.27 mA at the working frequency of 1,536 MHz. The algorithm is verified using MATLAB for different possible obstacles and percentage error has been calculated for each case. The hardware of this sensor node processor has been realised using ISE 14.3 simulation tools and emulated in Virtex-V prototype field programmable gate array kit.

Keywords: wireless sensor networks; WSNs; beacon; obstacle localisation; pulse mode object localisation; power efficiency; high performance; wireless networks; very large scale integrated; VLSI; routing; delay; energy consumption; sleep scheduling; simulation; field programmable gate arrays; FPGA.

DOI: 10.1504/IJHPSA.2013.058982

International Journal of High Performance Systems Architecture, 2013 Vol.4 No.4, pp.204 - 217

Received: 06 Apr 2013
Accepted: 28 Aug 2013
Published online: 25 Jul 2014 *

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