Title: Analysis and design of 1 GHz PLL for fast phase and frequency acquisition

Authors: Prakash Kumar Rout; Bibhu Prasad Panda; Debiprasad Priyabrata Acharya; Ganapati Panda

Addresses: Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela 769008, India ' Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela 769008, India ' Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela 769008, India ' School of Electrical Engineering, Indian Institute of Technology, Bhubaneswar, India

Abstract: Phase locked loop (PLL) being a mixed signal circuit involves design challenges at high frequencies. In this work a mixed signal PLL for faster phase and frequency locking is designed. The PLL is designed and synthesized using GPDK090 library of CMOS 90 nm process in CADENCE Virtuoso Analog Design Environment for an operating frequency of 1 GHz. Its locking time is 280.6 ns and observed to consume a power of 11.9 mW with a 1.8 V supply voltage. The complete layout of the PLL is drawn in CADENCE Virtuoso XL and its behaviour and performance is observed in Spectre.

Keywords: PFD; phase frequency detector; loop filter; VCO; voltage controlled oscillator; PLL; phase-locked loops; fast phase; frequency acquisition; circuit design.

DOI: 10.1504/IJSISE.2014.057938

International Journal of Signal and Imaging Systems Engineering, 2014 Vol.7 No.1, pp.30 - 37

Received: 05 Feb 2011
Accepted: 23 Apr 2011
Published online: 24 Oct 2014 *

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