Title: A survey of architectural techniques for DRAM power management

Authors: Sparsh Mittal

Addresses: Electrical and Computer Engineering, Iowa State University, Iowa, 50014, USA

Abstract: Recent trends of CMOS technology scaling and wide-spread use of multicore processors have dramatically increased the power consumption of main memory. It has been estimated that modern data-centres spend more than 30% of their total power consumption in main memory alone. This excessive power dissipation has created the problem of 'memory power wall' which has emerged as a major design constraint inhibiting further performance scaling. Recently, several techniques have been proposed to address this issue. The focus of this paper is to survey several architectural techniques designed for improving power efficiency of main memory systems, specifically DRAM systems. To help the reader in gaining insights into the similarities and differences between the techniques, this paper also presents a classification of the techniques on the basis of their characteristics. The aim of this paper is to equip the engineers and architects with knowledge of the state of the art DRAM power saving techniques and motivate them to design novel solutions for addressing the challenges presented by the memory power wall problem.

Keywords: architectural techniques; power efficiency; DRAM energy saving; DRAM power management; DRAM energy management; main memory; survey; review; classification; system architecture; power consumption; DRAM power saving; memory power wall.

DOI: 10.1504/IJHPSA.2012.050990

International Journal of High Performance Systems Architecture, 2012 Vol.4 No.2, pp.110 - 119

Received: 09 Aug 2012
Accepted: 07 Sep 2012

Published online: 02 Sep 2014 *

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