Title: Mixing static and dynamic strategies for high performance and low area reconfigurable systems

Authors: Mateus Beck Rutzig; Antonio Carlos Schneider Beck

Addresses: Computer Science Program, Informatics Institute, Federal University of Rio Grande do Sul, Bento Gonçalves 9500 – Setor IV, Porto Alegre, Brazil. ' Computer Science Program, Informatics Institute, Federal University of Rio Grande do Sul, Bento Gonçalves 9500 – Setor IV, Porto Alegre, Brazil

Abstract: Reconfigurable architectures can be seen as a possible solution to increase performance of current embedded systems. While dynamic reconfigurable systems present different degrees of adaptability at the price of huge area overhead, static exploitation tools can be used at design time to generate a tailored reconfigurable unit with small area requirements. However, the speedup using static tools will be limited only to the specific application set previously analysed. Therefore, we propose a technique that presents the best compromise between both approaches. After a high performance and low-power reconfigurable unit, optimised in area, is produced by a static exploitation tool, it is coupled to a dynamic hardware mechanism responsible for accelerating applications not foreseen at design time. Hence, both the capability of adaptation and the binary compatibility are maintained. We are able to save up to 40% in area and 77% in power, without significant losses in performance or adaptability.

Keywords: reconfigurable hardware; reconfigurable computing; high performance architecture; reconfigurable processors; ALU array architecture; data flow graphs; power consumption; energy consumption.

DOI: 10.1504/IJHPSA.2012.047567

International Journal of High Performance Systems Architecture, 2012 Vol.4 No.1, pp.13 - 24

Received: 29 Jul 2011
Accepted: 21 Feb 2012
Published online: 02 Sep 2014 *

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