Title: Monitoring transaction level SystemC models using a generic and aspect-oriented framework

Authors: Meriam Kallel; Younes Lahbib; Adel Baganne; Rached Tourki

Addresses: EµE Lab, Faculty of Sciences of Monastir, Bd. de l'environnement, 5019, Monastir, Tunisia; Lab-Sticc CNRS, UBS University, BP 92116, 56321 Lorient, France. ' EµE Lab, Faculty of Sciences of Monastir, Bd. de l'environnement, 5019, Monastir, Tunisia. ' Lab-Sticc CNRS, UBS University, BP 92116, 56321 Lorient, France. ' EµE Lab, Faculty of Sciences of Monastir, Bd. de l'environnement, 5019, Monastir, Tunisia

Abstract: Transaction level modelling (TLM) is gaining acceptance as a way to create hardware designs at high abstraction levels. It allows better simulation performances and early prototyping for system-on-chip (SoC) designs. Transaction level models are therefore increasingly being used as golden references. In this paper, we present a new framework for the verification of properties of SystemC transaction level models during simulation. Functional as well as performance properties are addressed. Aspect-oriented programming (AOP) techniques are exploited to monitor the design under verification in an automated way and to write assertion checkers that fit TLM requirements. In addition, we propose a generic SystemC implementation approach that allows the specification and validation of fully-parameterisable transaction level properties. We illustrate our work on a realistic multi-level SoC platform based on the TLM-2.0 standard and including Open Core Protocol (OCP) interfaces.

Keywords: simulation; model verification; system-on-chip; SoC design; transaction level modelling; TLM; assertions; aspect-oriented programming; AOP; SystemC; hardware design; high abstraction.

DOI: 10.1504/IJCAET.2012.046635

International Journal of Computer Aided Engineering and Technology, 2012 Vol.4 No.3, pp.229 - 249

Published online: 16 Aug 2014 *

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