Int. J. of Information Technology, Communications and Convergence   »   2011 Vol.1, No.4

 

 

Title: Design space exploration for low-power channel decoder in embedded LDPC-H.264 joint decoding architecture

 

Authors: Yoon Seok Yang; Gwan Choi

 

Addresses:
Department of Electrical and Computer Engineering, Texas A&M University, College Station, Texas 77843, USA.
Department of Electrical and Computer Engineering, Texas A&M University, College Station, Texas 77843, USA

 

Abstract: This paper presents a low-power design scheme to lower baseband energy consumption using joint source decoding and dynamic voltage and frequency scaling (DVFS). This scheme combines unequal error protection (UEP) developed for error resilient video coding with a variable iteration low density parity check (LDPC) decoder to trade off performance against energy consumption. Using the proposed method, we determine LDPC decoding configurations that achieve minimum energy consumption while satisfying prespecified image quality at the receiver. The implementation results yield 17%, 37%, 52% power reductions with 0, 0.3, 1.1 dB peak signal to noise ratio (PSNR) degradation at 3.6 dB SNR in Foreman test stream respectively.

 

Keywords: low-power channel decoders; search method; joint source-channel decoding; unequal error protection; UEP; dynamic voltage and frequency scaling; DVFS; H.264 data partitioning; low density parity check; LDPC; energy consumption; video coding.

 

DOI: 10.1504/IJITCC.2011.044641

 

Int. J. of Information Technology, Communications and Convergence, 2011 Vol.1, No.4, pp.372 - 390

 

Available online: 30 Dec 2011

 

 

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