Title: PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model

Authors: Edson P. Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Mauricio Perretto

Addresses: Department of Computer Engineering, Positivo University, Rua Prof. Pedro V.P. de Souza, 5300 81280-330 Curitiba (PR), Brazil. ' Department of Electronics, Federal University of Technology – Parana, Av. 7 de setembro, 3165 80230-901 Curitiba (PR), Brazil. ' Department of Electronics, Federal University of Technology – Parana, Av. 7 de setembro, 3165 80230-901 Curitiba (PR), Brazil. ' Department of Computer Engineering, Positivo University, Rua Prof. Pedro V.P. de Souza, 5300 81280-330 Curitiba (PR), Brazil

Abstract: This work proposes and implements a reconfigurable parallel architecture based on dataflow for numerical computation, named PRADA. This architecture uses concepts of parallel processing to obtain a scalable performance and the dataflow concept for controlling the parallel execution of instructions. PRADA is composed by a control unit and several processing elements (PEs). In the control unit, there are several functional blocks, including data and instruction memories. Each PE is composed by an ALU and buffers. PRADA is organised as a cluster, in which several independent dataflow modules are interconnected together. PRADA was developed in VHDL and implemented in reconfigurable hardware using a FPGA device. Therefore, it can offer high performance, scalability and customised solutions for engineering problems. Results of the application of PRADA to the computation of a digital filter and a cryptography algorithm are presented. Results are also compared with other different architectures, such as microprocessors, ASICs, DSPs, reconfigurable architectures and dataflow architectures. In most cases, PRADA achieved either competitive or higher performance than the other architectures, regarding the measures used. Overall results suggest that this architecture can be applied to several classes of problems that may require a high throughput, such as cryptography, optimisation and scientific computing.

Keywords: parallel architectures; reconfigurable computing; high performance architecture; dataflow modelling; parallel processing; scalable performance; clusters; VHDL; reconfigurable hardware; FPGA devices; field-programmable gate arrays; digital filters; cryptography; optimisation; scientific computing.

DOI: 10.1504/IJHPSA.2011.038057

International Journal of High Performance Systems Architecture, 2011 Vol.3 No.1, pp.41 - 55

Received: 27 Aug 2009
Accepted: 24 Feb 2010

Published online: 21 Mar 2015 *

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