Title: If-conversion for embedded VLIW architectures

Authors: C. Bruel

Addresses: ST Microelectronics, 12 rue Jules Horowitz, 38000 Grenoble, France

Abstract: If-conversion refers to a compiler optimisation that eliminates conditional branches by transforming a control flow region into an equivalent set of conditional instructions. VLIW architectures, used in the design of embedded multimedia processors, can support predicated execution with a limited number of conditional instructions or a full predicated ISA. We present in this paper a speculation framework and a set of Single Static Assignment (SSA) transformations to incrementally build if-converted regions on architectures supporting the select model of conditional moves. This framework has been further extended to support a configurable set of predicated instructions and used to explore architectural variants with predicated memory instructions. We implemented this SSA if-conversion algorithm in the Open64 code generator for the ST231 processor. We show an average cycles improvement of 31% without code size penalty.

Keywords: VLIW architectures; if-conversion; compiler controlled speculation; partial predication; instruction level parallelism; SSA transformations; single static assignment; embedded systems; very long instruction word; compiler optimisation.

DOI: 10.1504/IJES.2009.027236

International Journal of Embedded Systems, 2009 Vol.4 No.1, pp.2 - 16

Published online: 18 Jul 2009 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article