Title: Time-shared AES-128 implementation with extremely low-cost for smart card applications

Authors: P. Saravanan; S. Shanthi Rekha

Addresses: Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore – 641 004, Tamil Nadu, India ' Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore – 641 004, Tamil Nadu, India

Abstract: Smart cards have seen tremendous growth in the past few years due to their multiple functions delivering ability. They can be used for personal identification, healthcare applications, financial applications, etc. Smart cards contain an embedded circuit that stores and processes a large amount of data. One of the key function performed by the circuit is the cryptographic operation namely encryption. Since these devices are resource constrained, low-cost implementations of cryptographic algorithms are desirable. Advanced encryption standard (AES) is one of the standard encryption algorithm proposed by NIST and is proved to be a suitable candidate for secure and lightweight implementations on hardware compared to its other symmetric counterparts. This work proposes a novel low-cost implementation of AES-128 algorithm using time-shared architectures for contactless smart card applications. The proposed architecture reuses the primitives in a twofold mechanism leading to a novel resource efficient architecture on an FPGA platform.

Keywords: smart cards; advanced encryption standard; cryptography; low-cost implementation; throughput; resource constrained; VLSI implementation; information security; time-shared architecture.

DOI: 10.1504/IJICS.2021.118951

International Journal of Information and Computer Security, 2021 Vol.16 No.3/4, pp.239 - 254

Received: 30 Nov 2017
Accepted: 30 Dec 2018
Published online: 15 Nov 2021 *

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