Title: Divide-by-16/17 dual modulus prescaler design with enhanced speed in a 180nm CMOS technology

Authors: Uma Nirmal; V.K. Jain

Addresses: College of Engineering and Technology, Mody University of Science and Technology, Lakshmangarh, 332311, India ' College of Engineering and Technology, Mody University of Science and Technology, Lakshmangarh, 332311, India

Abstract: In this work, we propose a high-speed dual modulus divide by 16/17 prescaler Design IV with 8.9 GHz operating rate. It uses RE-3 type DFF in synchronous divide by 2/3 prescaler design and asynchronous divide by 8 counter design. It reduces: design complexity, capacitive loading and delay. The proposed Design IV shows better results in terms of both speed and power performance than other ratioed and ratioless divide by 16/17 prescalers. It is implemented in a 180 nm CMOS technology and consumes only 0.38 mW power from a 1V supply voltage. The speed of the new Design IV is improved by ~53% compared with conventional circuits with operating frequency 5.8 GHz.

Keywords: divide by 16/17 DMP; DMP; true-single phase-clock; TSPC; D flip flop; DFF; RE-0; RE-1; RE-2; RE-3; RE-4.

DOI: 10.1504/IJCAET.2021.114490

International Journal of Computer Aided Engineering and Technology, 2021 Vol.14 No.3, pp.345 - 357

Received: 15 Jun 2018
Accepted: 07 Aug 2018
Published online: 26 Apr 2021 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article