The full text of this article/chapter:
Dynamically reconfigurable processor for multimedia application
by Hrvoje Mlinaric, Kresimir Duracic, Mario Kovac
12th International Workshop on Systems, Signals and Image Processing (IWSSIP), Vol. 1, No. 1, 2005
Abstract: This paper presents a dynamically reconfigurable processor designed for processing data in multimedia application. The work was done as resource of PhD. Research and years of experience in processor architecture and multimedia audio and video application design. The object of this research is to build a high performance reconfigurable processor providing highly scalable architecture and transparent hardware reconfigurable for the multimedia application such as, video encoding/decoding, audio encoding/decoding, speech encoding/decoding.
is only available to individual subscribers or to users at subscribing institutions.
Pay per view: If you are not a Subscriber and you just want to read the full contents of this article, please click here to purchase online access to the full-text of this article. Please allow 3 days + mailing time. Current price for article is US$38.00
Members of the Editorial Board or subscribers of the 12th International Workshop on Systems, Signals and Image Processing (IWSSIP), that have been redirected here, please click here if you have IP-authentication access, or check if you have a registered username/password subscription with Inderscience. If that is the case, please Login: