Design of a parity preserving reversible full adder/subtractor circuit
by Shiva Rahbar Arabani; Mohammad Reza Reshadinezhad; Majid Haghparast
International Journal of Computational Intelligence Studies (IJCISTUDIES), Vol. 7, No. 1, 2018

Abstract: The reversible logical circuits, due to their economised power consumption in comparison with their counterparts with binary circuits, have become a major issue of study. A reversible circuit with equal parity of inputs and outputs is considered as a parity preserving circuit. In such circuits, any fault effecting only one logical signal, is detectable at the main outputs. A new 5 × 5 parity preserving reversible block called RRH is proposed which would operate as a half adder/subtractor and a full adder/subtractor. The outcome of comparisons indicates that this proposed block outperforms its counterparts with respect to the number of constant inputs and garbage outputs, quantum cost and circuit dimensions.

Online publication date: Fri, 02-Mar-2018

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