Intelligent selective modular redundancy for online fault detection of adders in FPGA
by Jisha M. Nair; C. Pradeep
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 6, No. 4, 2016

Abstract: Developments in VLSI technology have enabled single chip to perform complex functionalities. The increase in density of VLSI chip has necessitated online fault detection technique to increase reliability of digital systems. This paper proposes a data dependent technique of online fault detection for adder architectures. The type of data inputs to adder circuit are used efficiently to design an area optimised technique. The developed technique is capable of detecting single stuck-at faults that occur in an adder using two rail checker. A comparison is made by implementing the design in different FPGA devices. The results show that the proposed data path has better device utilisation and less delay in Virtex5. The technique has 28% area overhead when applied to carry select adders.

Online publication date: Tue, 24-Jan-2017

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