Design and analysis of RF-low power and low-phase noise CMOS ring oscillator for fully integrated RF communication systems technologies Online publication date: Tue, 15-Dec-2015
by Ashish Raman; Rakesh Kumar Sarin
International Journal of Information and Communication Technology (IJICT), Vol. 8, No. 1, 2016
Abstract: This manuscript presents the design and analysis of five-stage, low power ring oscillator. The ring oscillator has implemented in 0.18 µm CMOS one-poly six-metal-layer process technology and designed for frequency synthesiser module used in RF communication applications. This work uses a single ended topology and the delay cell is designed with both tail-ahead and tail-current concept for frequency improvement. This work projects the effect of transistor size (w/l) on the important parameters of oscillator viz. frequency and power dissipation. Measurements show that the oscillator covers a frequency range of 0.9-2 GHz. Their analyses demonstrate that the circuit consumes minimum power of 305 µW at 0.9 GHz and maximum 575 µW at 2 GHz oscillating frequency. The designed oscillator occupies an area of 296 * 130 µm² and manifest an improved phase noise level of −111.9 dBc/Hz.
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Information and Communication Technology (IJICT):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email subs@inderscience.com
Our Blog 
Follow us on Twitter 
Visit us on Facebook