Efficient implementation of Sobel edge detection algorithm on CPU, GPU and FPGA
by Marwa Chouchene; Fatma Ezahra Sayadi; Yahia Said; Mohamed Atri; Rached Tourki
International Journal of Advanced Media and Communication (IJAMC), Vol. 5, No. 2/3, 2014

Abstract: Many applications in image processing have high degrees of inherent parallelism and are thus good candidates for parallel implementation. In fact, programming tools for field programmable gate array (FPGA), SIMD instructions on CPU and a large number of cores on graphic processor unit (GPU) have been developed, but it is still difficult to achieve high performance on these platforms. This paper analyses the distinct features of compute unified device architecture (CUDA) GPU and summarises the general program mode of CUDA. Furthermore, we present three different implementations of Sobel edge detection on CPU, FPGA and GPU. Tested image data are also used in these hardware platforms to compare computational efficiency of CPU, GPU and FPGA.

Online publication date: Thu, 17-Apr-2014

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

 
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Advanced Media and Communication (IJAMC):
Login with your Inderscience username and password:

Username:        Password:          Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com