Intelligent speed controller for a Switched Reluctance Motor drive using FPGA Online publication date: Thu, 03-Sep-2009
by S. Vijayan, S. Paramasivam
International Journal of Intelligent Systems Technologies and Applications (IJISTA), Vol. 7, No. 4, 2009
Abstract: In this paper, an FPGA-based digital speed control scheme is presented to overcome the drawbacks in the previous speed control schemes, proposed for Switched Reluctance Motor (SRM) drives. It is based on discrete control algorithm, and requires simple mathematical models. The real-time experimental results given in this paper show that the closed-loop speed control method proposed could provide accurate speed control upto 6.2 rpm depending on the needed operating speed range, with a step response settling time of 0.25-1.05 s. It can also perform accurately at different operating conditions and over a wide range of speeds. Complete descriptions of the experimental system along with FPGA implementation are presented.
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Intelligent Systems Technologies and Applications (IJISTA):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email subs@inderscience.com