Off-loading application controlled data prefetching in numerical codes for multi-core processors
by J. Weidendorfer, C. Trinitis
International Journal of Computational Science and Engineering (IJCSE), Vol. 4, No. 1, 2008

Abstract: An important issue when designing numerical code in High Performance Computing is cache optimisation in order to exploit the performance potential of a given target architecture. This includes techniques to improve memory access locality as well as prefetching. Inherent algorithm constrains often limit the first approach, which typically uses a blocking technique. While there exist automatic prefetching mechanisms in hardware and/or compilers, they can not complement blocking with additional prefetching. We provide an infrastructure for off-loading application controlled prefetching on a chip multiprocessor, allowing to further improve numerical code already optimised by standard cache optimisation. Clear benefits are shown for real workloads on existing hardware.

Online publication date: Tue, 04-Nov-2008

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