Atomic-scale silicon device fabrication
by M.Y. Simmons, F.J. Ruess, K.E.J. Goh, W. Pok, T. Hallam, M.J. Butcher, T.C.G. Reusch, G. Scappucci, A.R. Hamilton, L. Oberbeck
International Journal of Nanotechnology (IJNT), Vol. 5, No. 2/3, 2008

Abstract: The driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce device sizes below 10 nm. In this paper we demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in combination with scanning probe lithography and high purity crystal growth. Using this process we have fabricated conducting nanoscale wires with widths down to ∼8 nm, and arrays of P-doped dots in silicon. We will present an overview of devices that have been made with this technology and highlight some of the detailed atomic level understanding of the doping process developed towards atomically precise devices.

Online publication date: Wed, 30-Jan-2008

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