Automatic localisation method for VLSI topology errors at the stage of functional control
by K.K. Smirnov; A.V. Nazarov; M.N. Ushkar
International Journal of Nanotechnology (IJNT), Vol. 16, No. 6/7/8/9/10, 2019

Abstract: The paper substantiates the urgency of the task of increasing the level of automation of functional testing of integrated structures that implement ultra-large integrated circuits (VLSI). To solve this task, there is proposed an original route designing and testing VLSI. This route for the first time implements the idea of automatically localising erroneous places in the topology of the integra structure. It is shown that the reasons for which up to now it was not possible to avoid developer intervention in the chain of operations of the "algorithm-topology of VLSI" cycle is to repeatedly convert formats and convert tests leading to the loss of debug information. The reasons for the loss of this information are analysed in detail and methods are proposed for restoring, more precisely, preventing informational disconnection between the mathematical and topological model of VLSI. To solve the problem of localisation of erroneous places in the VLSI topology, the paper presents a software and hardware complex based on the original software Functional Test Studio (FT Studio). FT Studio allows you to automate the verification of almost all types of VLSI, the composition of which is determined by the current standard OST B 11.073.012-87 "Integrated Circuits. Special general technical conditions", including qualification and VLSI test tests. Software FT Studio leads the route of functional control of microcircuits to a new, higher level of automation. At this route the connection of the mathematical and topological model of VLSI is preserved within of the unified information environment. The latter relies on a powerful apparatus of the original object- and hardware oriented language Smirnov Test Electrical Exposition Language (STeeL), which supports the multiplatform nature of technological equipment. For the implementation and maintenance of the communication between an algorithm and topology VLSI, there are using language of interoperative exchange RSTL and system for analysing the results of measurements "Lorenz", which perform automatic conversion and correct inter-unit information transfer from stage to stage.

Online publication date: Wed, 15-Apr-2020

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