Methods to ensure reliable contact of super-large integrated circuit with test equipment
by K.K. Smirnov; A.V. Nazarov; A.S. Borovov; M.N. Ushkar
International Journal of Nanotechnology (IJNT), Vol. 16, No. 6/7/8/9/10, 2019

Abstract: The design and technological problems arising from the use of contacting devices that connect an extra-large integrated circuit with test equipment during the testing process are considered. A review of the design and technological features of the contacting devices and an analysis of the causes of their main faults are given. Particular attention is paid to the analysis of the problems of the strength of the conclusions of the VLSI-chips implemented in BGA-cases. A method has been proposed that partially solves the problem of reducing the strength of the conclusions of a BGA-chip. It is shown that when high-speed interfaces are present in a chip, the maximum signal transfer rate is provided by the use of the Flip-Chip-technology for packaging ultra-large integrated circuits. A classification of contacting devices and of methods for their contacting with the chip is presented. An analysis of the advantages and disadvantages of contacting devices is given. Software and hardware complexes have been developed and a testing technique is proposed of contacting devices. Based on the test results, recommendations are proposed for choosing the most effective method of contacting ultra-large integrated circuits in FCBGA type housings with test equipment. The proposed methods of testing and hardware and software complexes allow you to test individually each of the hundreds of contacting devices with the chip being tested, that is, to obtain information on the failures of each contact.

Online publication date: Wed, 15-Apr-2020

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