Most recent issue published online in the International Journal of High Performance Systems Architecture.
International Journal of High Performance Systems Architecture
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International Journal of High Performance Systems Architecture
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International Journal of High Performance Systems Architecture
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http://www.inderscience.com/browse/index.php?journalID=213&year=2023&vol=11&issue=3
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Countermeasure SDN-based IoT threats using blockchain multicontroller
http://www.inderscience.com/link.php?id=130190
The Internet of Things (IoT) is making significant progress in various fields; software-defined networks with multiple controllers have become popular because they make it easier to manage large networks. But they are open to several attacks, which makes controller topologies inconsistent. To solve this problem, we suggest a multi-controller blockchain for software-defined networking (SDN) network. This security architecture combines blockchain and multi-controller SDN and divides the network into several domains. We put forth a blockchain-based solution. This paper proposed a model blockchain-enabled SDN multi-controller architecture for IoT networks that uses a clustering algorithm and a new routing protocol that is both secure and energy-efficient. Experimental results indicate that the cluster-based routing protocol has a greater capacity, a shorter response time, and a lower overall power requirement than other protocols. It has been shown that our proposed architecture outperforms the classic blockchain.
Countermeasure SDN-based IoT threats using blockchain multicontroller
K. Janani; S. Ramamoorthy
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 117 - 128
The Internet of Things (IoT) is making significant progress in various fields; software-defined networks with multiple controllers have become popular because they make it easier to manage large networks. But they are open to several attacks, which makes controller topologies inconsistent. To solve this problem, we suggest a multi-controller blockchain for software-defined networking (SDN) network. This security architecture combines blockchain and multi-controller SDN and divides the network into several domains. We put forth a blockchain-based solution. This paper proposed a model blockchain-enabled SDN multi-controller architecture for IoT networks that uses a clustering algorithm and a new routing protocol that is both secure and energy-efficient. Experimental results indicate that the cluster-based routing protocol has a greater capacity, a shorter response time, and a lower overall power requirement than other protocols. It has been shown that our proposed architecture outperforms the classic blockchain.]]>
10.1504/IJHPSA.2023.130190
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 117 - 128
K. Janani
S. Ramamoorthy
Department of Computing Technologies, SRM Institute of Science and Technology, Kattankulathur †603203, Tamil Nadu, India ' Department of Computing Technologies, SRM Institute of Science and Technology, Kattankulathur †603203, Tamil Nadu, India
adaptive fading reputation
IoT attacks
blockchain
IoT
SDN multicontroller
security
power consumption
cluster based routing protocol
2023-04-06T23:20:50-05:00
Copyright © 2023 Inderscience Enterprises Ltd.
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117
128
2023-04-06T23:20:50-05:00
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Efficient hardware implementation of SIMECK lightweight block cipher
http://www.inderscience.com/link.php?id=130224
The internet of things (IoT) has recently expanded, resulting in a new world of smart gadgets with substantial security consequences. For their vital security role, lightweight block ciphers have gained a significant amount of development in low resource devices (LRDs). SIMECK is a new lightweight block cipher family that incorporates the finest aspect of both SIMON and SPECK. SIMECK is a more efficient block cipher than SIMON and SPECK cipher. These lightweight ciphers are especially referred to as an alternative to the AES for RCD. In this study, area optimised architecture is implemented for SIMECK lightweight block cipher with sizes: 64/128. For implementation on different platforms such as Sparton-6, Sparton-3, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA are used to examine several properties such as block size, key scheduling, and throughput, among others. The proposed area optimised architecture have attained a maximum operating frequency of 496.429 MHz with 61 slices and a high throughput of 706.032 Mbps on the Virtex-7 platform.
Efficient hardware implementation of SIMECK lightweight block cipher
Shweta Kumari; Zeesha Mishra; Bibhudendra Acharya
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 129 - 136
The internet of things (IoT) has recently expanded, resulting in a new world of smart gadgets with substantial security consequences. For their vital security role, lightweight block ciphers have gained a significant amount of development in low resource devices (LRDs). SIMECK is a new lightweight block cipher family that incorporates the finest aspect of both SIMON and SPECK. SIMECK is a more efficient block cipher than SIMON and SPECK cipher. These lightweight ciphers are especially referred to as an alternative to the AES for RCD. In this study, area optimised architecture is implemented for SIMECK lightweight block cipher with sizes: 64/128. For implementation on different platforms such as Sparton-6, Sparton-3, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA are used to examine several properties such as block size, key scheduling, and throughput, among others. The proposed area optimised architecture have attained a maximum operating frequency of 496.429 MHz with 61 slices and a high throughput of 706.032 Mbps on the Virtex-7 platform.]]>
10.1504/IJHPSA.2023.130224
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 129 - 136
Shweta Kumari
Zeesha Mishra
Bibhudendra Acharya
Department of Electronics and Communication Engineering, National Institute of Technology Raipur, CG, 492010, India ' Department of Microelectronics and VLSI, CSVTU Bhilai, Durg, 491107, India ' Department of Electronics and Communication Engineering, National Institute of Technology Raipur, CG, 492010, India
lightweight cryptography
resource constrained devices
IoT
internet of things
low resource devices
FРGА
field programmable gate array
advanced encryption standard
2023-04-06T23:20:50-05:00
Copyright © 2023 Inderscience Enterprises Ltd.
11
3
129
136
2023-04-06T23:20:50-05:00
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3D layout of the Spidergon-Donut on-chip interconnection network
http://www.inderscience.com/link.php?id=130222
3D integration promises to resolve many of the heat and die size limitations of 2D integrated circuits. A critical step in the design of 3D many-cores and MPSOCs is the layout of their 3D network-on-chip (NoC). In this paper, we explore and present multiple 3D layouts of the Spidergon-Donut (SD) NoC and estimate their longest wire lengths and cost requirements. For a total of 64 cores, the 4×2×8 and 2×4×8 placements result in the best longest wire delays, with the former higher 3D integration costs, while the second requiring larger chip area and through-silicon-vias (TSV) array costs. Such study helps in guiding 3D integration direction and weighing 3D NoC layout and placement alternatives.
3D layout of the Spidergon-Donut on-chip interconnection network
Fadi N. Sibai; Abu Asaduzzaman; Ali Elmoursy
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 137 - 147
3D integration promises to resolve many of the heat and die size limitations of 2D integrated circuits. A critical step in the design of 3D many-cores and MPSOCs is the layout of their 3D network-on-chip (NoC). In this paper, we explore and present multiple 3D layouts of the Spidergon-Donut (SD) NoC and estimate their longest wire lengths and cost requirements. For a total of 64 cores, the 4×2×8 and 2×4×8 placements result in the best longest wire delays, with the former higher 3D integration costs, while the second requiring larger chip area and through-silicon-vias (TSV) array costs. Such study helps in guiding 3D integration direction and weighing 3D NoC layout and placement alternatives.]]>
10.1504/IJHPSA.2023.130222
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 137 - 147
Fadi N. Sibai
Abu Asaduzzaman
Ali Elmoursy
Department of Electrical & Computer Engineering, Gulf University for Science and Technology, P.O. Box 7207, Hawally 32093, Kuwait ' Department of Electrical and Computer Engineering, Wichita State University, Wichita, KS 67260, USA ' Department of Electrical and Computer Engineering, University of Sharjah, P.O. Box 27272, Sharjah, UAE
3D integration
3D on-chip networks
Spidergon-Donut network
many-core processors
wire delay
chip area
heat dissipation
2023-04-06T23:20:50-05:00
Copyright © 2023 Inderscience Enterprises Ltd.
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137
147
2023-04-06T23:20:50-05:00
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High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit
http://www.inderscience.com/link.php?id=130225
Some of the advantages of the DC-DC converter digital control, such as programmability and improved control algorithms, have made it more popular in modern times. As a significant part of digital control, digital pulse width modulator (DPWM) is designed to fulfill number of requirements for high efficiency. The existing DPWM framework is implemented with high resolution along high switching frequency, but mandatory counter clock frequency is higher. To manipulate this drawback, the hybrid DPWM architecture is proposed that consolidates reversible synchronous sequential counter (RSSC) and synchronous phase-shifted circuit (SPS). The RSSC is employed to count trigger signal at each clock period. Whereas, SPS circuit is employed to select the clock by the quadrant phase-shifted clocks. The coding is activated in Verilog and the proposed RSSC design is synthesised utilising Xilinx ISE.
High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit
S.K. Binu Siva Singh; K.V. Karthikeyan
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 148 - 155
Some of the advantages of the DC-DC converter digital control, such as programmability and improved control algorithms, have made it more popular in modern times. As a significant part of digital control, digital pulse width modulator (DPWM) is designed to fulfill number of requirements for high efficiency. The existing DPWM framework is implemented with high resolution along high switching frequency, but mandatory counter clock frequency is higher. To manipulate this drawback, the hybrid DPWM architecture is proposed that consolidates reversible synchronous sequential counter (RSSC) and synchronous phase-shifted circuit (SPS). The RSSC is employed to count trigger signal at each clock period. Whereas, SPS circuit is employed to select the clock by the quadrant phase-shifted clocks. The coding is activated in Verilog and the proposed RSSC design is synthesised utilising Xilinx ISE.]]>
10.1504/IJHPSA.2023.130225
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 148 - 155
S.K. Binu Siva Singh
K.V. Karthikeyan
Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Jeppiaar Nagar, Chennai †100119, Tamil Nadu, India ' Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Jeppiaar Nagar, Chennai †100119, Tamil Nadu, India
DPWM
digital pulse width modulator
decoder
synchronous reversible counter
synchronous phase shifted circuit
reversible synchronous sequential counter
D-flip flop
delay line output duty cycle
linearity
time resolution
2023-04-06T23:20:50-05:00
Copyright © 2023 Inderscience Enterprises Ltd.
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148
155
2023-04-06T23:20:50-05:00
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MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application
http://www.inderscience.com/link.php?id=130214
The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.
MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application
Prashant S. Titare; D.G. Khairnar
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 156 - 168
The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.]]>
10.1504/IJHPSA.2023.130214
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 156 - 168
Prashant S. Titare
D.G. Khairnar
E&TC Department, D Y Patil College of Engineering, Akurdi, Pune, 411044, India ' E&TC Department, D Y Patil College of Engineering, Akurdi, Pune, 411044, India
multiprocessors
soft core processor architecture
embedded systems
VLSI
versions like ultra large
MPSoC
multi-processor system on chip
parallel processing
FPGA
field programmable gate array
high performance
speed enhancement
arithmetic application
2023-04-06T23:20:50-05:00
Copyright © 2023 Inderscience Enterprises Ltd.
11
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156
168
2023-04-06T23:20:50-05:00
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Hardware implementations of LBlock and XXTEA lightweight block ciphers for resource-constrained IoT application
http://www.inderscience.com/link.php?id=130223
Recent growth in the number of connected Internet of Things (IoT) devices in a network has raised lot of security related issues. Since these devices are mostly battery powered, have low memory and weak computational capability, therefore lightweight ciphers are the most suitable choice for providing security. Among various lightweight ciphers available, we have chosen to implement corrected block TEA (XXTEA) and LBlock ciphers. These lightweight ciphers are feistel based, having simple encryption algorithms. In this work, two different architectures are proposed namely round-based implementation of LBlock cipher and serial implementation of XXTEA cipher with variable length message. Both the architectures are implemented on different field programmable gate array (FPGA) device families and application-specific integrated circuit (ASIC) implementation is performed on 0.18 μm complementary metal-oxide semiconductor (CMOS) technology. By analysing the performance metrics, comparison of the proposed work is done with the existing ciphers. For the proposed LBlock and XXTEA variable length architectures, the percentage improvement obtained with respect to area consumption is 50.92% and 26.04% respectively.
Hardware implementations of LBlock and XXTEA lightweight block ciphers for resource-constrained IoT application
Apeksha Kamble; Zeesha Mishra; Bibhudendra Acharya
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 169 - 178
Recent growth in the number of connected Internet of Things (IoT) devices in a network has raised lot of security related issues. Since these devices are mostly battery powered, have low memory and weak computational capability, therefore lightweight ciphers are the most suitable choice for providing security. Among various lightweight ciphers available, we have chosen to implement corrected block TEA (XXTEA) and LBlock ciphers. These lightweight ciphers are feistel based, having simple encryption algorithms. In this work, two different architectures are proposed namely round-based implementation of LBlock cipher and serial implementation of XXTEA cipher with variable length message. Both the architectures are implemented on different field programmable gate array (FPGA) device families and application-specific integrated circuit (ASIC) implementation is performed on 0.18 μm complementary metal-oxide semiconductor (CMOS) technology. By analysing the performance metrics, comparison of the proposed work is done with the existing ciphers. For the proposed LBlock and XXTEA variable length architectures, the percentage improvement obtained with respect to area consumption is 50.92% and 26.04% respectively.]]>
10.1504/IJHPSA.2023.130223
International Journal of High Performance Systems Architecture, Vol. 11, No. 3 (2023) pp. 169 - 178
Apeksha Kamble
Zeesha Mishra
Bibhudendra Acharya
Department of Electronics and Communication Engineering, National Institute of Technology Raipur, Chhattisgarh †492010, India ' Department of Microelectronics and VLSI, UTD, Chhattisgarh Swami Vivekananda Technical University, Bhilai, Chhattisgarh †491107, India ' Department of Electronics and Communication Engineering, National Institute of Technology Raipur, Chhattisgarh †492010, India
IoT
Internet of Things
LWC
lightweight ciphers
LBlock
XXTEA
corrected block TEA
FPGA
field programmable gate array
ASIC
application-specific integrated circuit
block cipher
2023-04-06T23:20:50-05:00
Copyright © 2023 Inderscience Enterprises Ltd.
11
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169
178
2023-04-06T23:20:50-05:00