Most recent issue published online for the International Journal of High Performance Systems Architecture.

A minimalist cache coherent MPSoC designed for FPGAs

Jorge Tortato Junior — 2011-05-30T23:20:50-05:00

A minimalist cache coherent MPSoC designed for FPGAs
Jorge Tortato Junior, Roberto A. Hexsel
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 67 - 76
We describe the design and VHDL implementation of a cache coherent MPSoC named minimalist cache coherent MPSoC (MCCM). The system comprises one to eight MIPS-I processors, coherent primary data caches, memory management units, memory controller and the interconnection. We present a detailed account of the implementation, focusing on the shared memory subsystem. A simple benchmark is used to assess the overall system functionality. We compared the size of our design to that of a LEON3-based multiprocessor and found that a four-core LEON3 system needs roughly the same amount of logic/state as a six to eight cores MCCM.

Dynamic workload balancing deques for branch and bound algorithms in the message passing interface

Stefano Mor — 2011-05-30T23:20:50-05:00

Dynamic workload balancing deques for branch and bound algorithms in the message passing interface
Stefano Mor, Nicolas Maillard
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 77 - 86
The message passing interface (MPI) is the standard in message passing parallel computation. MPI does not provide a canonical way to dynamically distribute run-time generated workload evenly across all the participating computer nodes. This paper proposes a MPI library to provide near-optimal dynamical workload balancing over branch and bound (B&B) algorithms; B&B potentially produces huge workload unbalance during a parallel execution. The library, named RaWSDM, provides a double ended queue (deque) data structure on which the programmer may pop, process, and later, pull back some parallel tasks; an underlying efficient system scheduler is responsible for keeping the workload balanced by exchanging elements among all deques. Theoretical bounds are traced and practical experiments are performed with the unlimited knapsack problem. Results show a performance gain up to 80% (best-case scenario) against a pure MPI implementation using round-robin scheduling, with near linear speedup and memory consumption.

Challenges and solutions to improve the scalability of an operational regional meteorological forecasting model

Alvaro L. Fazenda — 2011-05-30T23:20:50-05:00

Challenges and solutions to improve the scalability of an operational regional meteorological forecasting model
Alvaro L. Fazenda, Jairo Panetta, Daniel M. Katsurayama, Luiz F. Rodrigues, Luis F.G. Motta, Philippe O.A. Navaux
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 87 - 97
This work investigates the parallel scalability of BRAMS, a limited area weather forecasting production code, from O(100) cores to O(1,000) cores on large grids (20 km and 10 km resolution runs over South America). Initial experiments show lack of scalability at modest core count. Execution time profiling and source code examination revealed the causes of the limited scalability: sequential algorithms and extensive memory requirements at scarcely used phases of the computation. As processor count increases, these 'secondary' phases dominate execution time. Algorithm replacement and memory reduction generate a new code version that possesses strong and weak scaling. The new version achieved a speed-up of 6 from 100 to 700 processors on the 20 km resolution grid and a speed-up of 6.9 on the same processor range on the 10 km resolution grid. Results were confirmed at another machine with a distinct architecture. Further experiments show that the scalability of the 20 km resolution case is limited by load unbalancing at the most demanding computational phase.

Automated refactorings for high performance Fortran programmes

Bruno Batista Boniati — 2011-05-30T23:20:50-05:00

Automated refactorings for high performance Fortran programmes
Bruno Batista Boniati, Andrea Schwertner Charao, Benhur De Oliveira Stein, Gustavo Rissetti, Eduardo Kessler Piveta
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 98 - 109
Refactoring is a software engineering technique aimed at improving the design of software applications, without changing their external behaviour. Several refactorings have been proposed for object-oriented languages, but there are few related works focusing on procedural programming. Fortran is a procedural language heavily used in high performance computing, which is not fully explored considering refactoring support. In this paper, we describe a set of automated refactorings for Fortran based on the Photran plug-in, which is integrated with the Eclipse integrated development environment (IDE). We present a set of experiments to evaluate the impact of the proposed refactorings in third-party Fortran applications. The results show that the proposed refactorings improve the design of existing applications without compromising their performance.

Assessing the influence of data access patterns and contention management policies on the performance of software transactional memory systems

Fernando Kronbauer — 2011-05-30T23:20:50-05:00

Assessing the influence of data access patterns and contention management policies on the performance of software transactional memory systems
Fernando Kronbauer, Sandro Rigo
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 110 - 121
Transactional memory was proposed as a mean for easing the burden of traditional concurrency control mechanisms. The programmer has only to mark the code sections that are to be executed atomically, and the system takes care of the synchronisation details. As transactions are executed in parallel, some of them are likely to access resources in ways that cannot be conciliated. Conflicts among transactions are mediated by a contention manager. In this work, we present a novel approach to contention management (CM), which binds different CM strategies to different data in a programme, based on the access patterns to these data. We show how it can be done in a way that introduces minimum overhead and present benchmark results to evaluate our implementation, also demonstrating how the best CM strategy may vary under different levels of contention, under a varying number of threads per processing core, and under different system architectures.

The impact of applications' I/O strategies on the performance of the Lustre parallel file system

Francieli Zanon Boito — 2011-05-30T23:20:50-05:00

The impact of applications' I/O strategies on the performance of the Lustre parallel file system
Francieli Zanon Boito, Rodrigo Virote Kassick, Philippe O.A. Navaux
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 122 - 136
Parallel applications present multiple approaches regarding the management of data. Due to specific characteristics of parallel file systems, some approaches will provide better performance than others due to a better matching to the system's internals. One common situation is when each instance of an application accesses exclusive data stored in the file system. This paper studies some I/O techniques for this situation and evaluates them on the Lustre file system. We provide a guide to help developers tune their application to extract the best performance out of Lustre. Our results show expressive gains in performance related with the choice of access pattern of the application. We present considerations on operation granularity, intra-node concurrency and temporal behaviour of the application.

Trebuchet: exploring TLP with dataflow virtualisation

Tiago A.O. Alves — 2011-05-30T23:20:50-05:00

Trebuchet: exploring TLP with dataflow virtualisation
Tiago A.O. Alves, Leandro A.J. Marzulo, Felipe M.G. Franca, Vitor Santos Costa
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 137 - 148
Parallel programming has become mandatory to fully exploit the potential of multi-core CPUs. The dataflow model provides a natural way to exploit parallelism. However, specifying dependences and control using fine-grained instructions in dataflow programs can be complex and present unwanted overheads. To address this issue, we have designed TALM: a coarse-grained dataflow execution model to be used on top of widespread architectures. We implemented TALM as the Trebuchet virtual machine for multi-cores. The programmer identifies code blocks that can run in parallel and connects them to form a dataflow graph, which allows one to have the benefits of parallel dataflow execution in a Von Neumann machine, with small programming effort. We parallelised a set of seven applications using our approach and compared with OpenMP implementations. Results show that Trebuchet can be competitive with state-of-the-art technology, while providing the benefits of dataflow execution.

A RISC architecture for 2DLNS-based signal processing

M. Azarmehr — 2011-05-30T23:20:50-05:00

A RISC architecture for 2DLNS-based signal processing
M. Azarmehr, R. Muscedere
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 149 - 156
The multi-dimensional logarithmic number system (MDLNS) provides a reduction in the size of the number representation and promises a lower cost realisation of arithmetic operations. The non-linear nature of the representation and independency of the parallel-based computations combined with multi-digit extensions of the MDLNS representations along with simplified arithmetic operations, make MDLNS suitable for some multiplication intensive DSP applications. The work presented in this paper is the design and implementation of a 2DLNS-based processor architecture. This CPU takes advantage of a relatively simple architecture and a well designed organisation which greatly improves the implementation of many DSP algorithms. An assembly programme is also written to implement a 2DLNS-based filterbank architecture. This implementation demonstrates the efficiency and ease of use of 2DLNS CPU in real applications.

GNLS: a hybrid on-chip communication architecture for SoC designs

Ling Wang — 2011-05-30T23:20:50-05:00

GNLS: a hybrid on-chip communication architecture for SoC designs
Ling Wang, Chunda Ding, Shenghai Zhong, Jianwen Zhang
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 157 - 166
In this paper, we propose global network local bus (GNLS) communication architecture, where network interface is designed and DMA communication is given. We also study and compare the performance of bus-based and mesh-based with GNLS NoC-based infrastructure by theoretical analysis and simulation. It is shown that NoC-based infrastructure performs better than bus-based one in terms of latency when the number of flits contained in the packets exceeds certain threshold. In addition, GNLS-based infrastructure outperforms mesh-based one under the same condition, which verifies the correctness of the theoretical performance analysis. An example of design is given to show that the proposed architecture has better performance than bus, and Mesh based architecture.

A hardware architecture for subtractive clustering

Marcos Santana Farias — 2011-05-30T23:20:50-05:00

A hardware architecture for subtractive clustering
Marcos Santana Farias, Nadia Nedjah, Luiza De Macedo Mourelle
International Journal of High Performance Systems Architecture, Vol. 3, No. 2/3 (2011) pp. 167 - 173
Clustering algorithms are used extensively to organise and categorise abundant data. This paper describes the implementation of subtractive clustering algorithm in hardware. The solution developed in this paper seeks a hardware implementation to automatic and fast identification of cluster centres. This hardware proposed is generic so it can be used in any data classification problems, omnipresent in identification systems.