International Journal of Embedded Systems http://www.inderscience.com/browse/index.php?journalID=45&year=2010&vol=4&issue=3/4 Inderscience Publishers Ltd en-uk International Journal of Embedded Systems 1741-1068 1741-1076 © 2010 Inderscience Publishers Ltd editor@inderscience.com https://www.inderscience.com/images/files/coverImgs/ijes_scoverijes.jpg http://www.inderscience.com/browse/index.php?journalID=45&year=2010&vol=4&issue=3/4 http://www.inderscience.com/link.php?id=39021 Systems on Chip (SoC) can draw various benefits such as adaptability and efficient acceleration of compute-intensive tasks from the inclusion of reconfigurable hardware as a system component. Dynamic reconfiguration capabilities of current reconfigurable devices create an additional dimension in the temporal domain. During the design space exploration phase, overheads associated with reconfiguration and hardware/software interfacing need to be evaluated carefully in order to harvest the full potential of dynamic reconfiguration. In order to overcome the limits deriving by the increasing complexity and the associated workload to maintain such complex infrastructure, one possibility is to adopt self-adaptive and autonomic computing systems (Kephart and Chess, 2003). Self-adapting computer systems will be capable of adapting their behaviour and resources thousands of times a second to automatically find the best way to accomplish a given goal despite changing environmental conditions and demands. Moreover, it is a system able to configure, heal, optimise and protect itself without the need for human intervention. These capabilities would benefit the full range of computer systems, from embedded devices to servers to supercomputers. Scenarios where self-awareness will be particularly useful include: mobile technologies, cloud computing systems, adaptive and dynamic compilation, multi-core microarchitecture and novel operating systems. From reconfigurable architectures to self-adaptive autonomic systems
Marco Domenico Santambrogio
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 172 - 181
Systems on Chip (SoC) can draw various benefits such as adaptability and efficient acceleration of compute-intensive tasks from the inclusion of reconfigurable hardware as a system component. Dynamic reconfiguration capabilities of current reconfigurable devices create an additional dimension in the temporal domain. During the design space exploration phase, overheads associated with reconfiguration and hardware/software interfacing need to be evaluated carefully in order to harvest the full potential of dynamic reconfiguration. In order to overcome the limits deriving by the increasing complexity and the associated workload to maintain such complex infrastructure, one possibility is to adopt self-adaptive and autonomic computing systems (Kephart and Chess, 2003). Self-adapting computer systems will be capable of adapting their behaviour and resources thousands of times a second to automatically find the best way to accomplish a given goal despite changing environmental conditions and demands. Moreover, it is a system able to configure, heal, optimise and protect itself without the need for human intervention. These capabilities would benefit the full range of computer systems, from embedded devices to servers to supercomputers. Scenarios where self-awareness will be particularly useful include: mobile technologies, cloud computing systems, adaptive and dynamic compilation, multi-core microarchitecture and novel operating systems.

]]> 10.1504/IJES.2010.039021 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 172 - 181 Marco Domenico Santambrogio Dipartimento di Elettronica ed Informazione (DEI), Politecnico di Milano, Via Ponzio 34/5, Milano 20133, Italy; Computer Science and Artificial Intelligence Laboratory (CSAIL), Massachusetts Institute of Technology (MIT), 02139, Cambridge, USA reconfigurable architectures performance reconfiguration codesign runtime adaptability self-adaptive systems autonomic computing system on chip SoC. 2011-03-11T23:20:50-05:00 4 3/4 172 181 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39022 The use of modern field-programmable logic devices can help system designers achieve better cost-performance characteristics, in particular in the case of multi-task and multi-modal workloads. This is particularly true when the embedded systems are based on run-time and partially reconfigurable FPGA devices. Such devices permit a system to implement part of its functionality in virtual form, by storing circuits as configuration bit-streams. The use of such virtual components, however, imposes certain requirements on both the behaviour of the system as well as the components themselves. The work presented here analyses some of these requirements, and proposes a potential framework for designing embedded systems using virtual resources. Two examples of a system using virtual components are presented and the infrastructure overhead for supporting virtual components is analysed. It is found that such systems can be implemented efficiently, both in terms of hardware resources as well as timing performance. A framework of embedded reconfigurable systems based on re-locatable virtual components
Victor Dumitriu, Lev Kirischian
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 182 - 194
The use of modern field-programmable logic devices can help system designers achieve better cost-performance characteristics, in particular in the case of multi-task and multi-modal workloads. This is particularly true when the embedded systems are based on run-time and partially reconfigurable FPGA devices. Such devices permit a system to implement part of its functionality in virtual form, by storing circuits as configuration bit-streams. The use of such virtual components, however, imposes certain requirements on both the behaviour of the system as well as the components themselves. The work presented here analyses some of these requirements, and proposes a potential framework for designing embedded systems using virtual resources. Two examples of a system using virtual components are presented and the infrastructure overhead for supporting virtual components is analysed. It is found that such systems can be implemented efficiently, both in terms of hardware resources as well as timing performance.

]]> 10.1504/IJES.2010.039022 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 182 - 194 Victor Dumitriu Lev Kirischian Department of Electrical and Computer Engineering, Ryerson University, 350 Victoria Street, Toronto, ON, M5B 2K3, Canada. ' Department of Electrical and Computer Engineering, Ryerson University, 350 Victoria Street, Toronto, ON, M5B 2K3, Canada dynamic reconfiguration embedded systems field programmable gate arrays reconfigurable FPGA system design video processing virtual hardware component virtualisation virtual components. 2011-03-11T23:20:50-05:00 4 3/4 182 194 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39024 Hardware task placements in dynamically reconfigurable logic need to satisfy different goals such as high placement efficiency, low fragmentation of the reconfigurable logic, and minimisation of routing resources. There have been several placement algorithms proposed for each goal. Nevertheless, the algorithm can only satisfy one goal, which results in poor results in the other goal satisfactions. We propose a novel multi-objective hardware placement (MOHP) method such that all goals are satisfied and if there are conflicts a good trade off is obtained. MOHP is similar to share-based schedulers that try to adjust resource utilisations among different scheduling methods by varying the processor bandwidth. By applying MOHP to some examples, we find that MOHP approximates the best performance for each assessment criterion. Multi-objective placement of reconfigurable hardware tasks in real-time system
Chun-Hsien Lu, Hsiao-Win Liao, Pao-Ann Hsiung
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 195 - 203
Hardware task placements in dynamically reconfigurable logic need to satisfy different goals such as high placement efficiency, low fragmentation of the reconfigurable logic, and minimisation of routing resources. There have been several placement algorithms proposed for each goal. Nevertheless, the algorithm can only satisfy one goal, which results in poor results in the other goal satisfactions. We propose a novel multi-objective hardware placement (MOHP) method such that all goals are satisfied and if there are conflicts a good trade off is obtained. MOHP is similar to share-based schedulers that try to adjust resource utilisations among different scheduling methods by varying the processor bandwidth. By applying MOHP to some examples, we find that MOHP approximates the best performance for each assessment criterion.

]]> 10.1504/IJES.2010.039024 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 195 - 203 Chun-Hsien Lu Hsiao-Win Liao Pao-Ann Hsiung Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi – 621, Taiwan. ' Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi – 621, Taiwan. ' Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi – 621, Taiwan multiobjective hardware placement low fragmentation routing costs embedded systems real-time tasks reconfigurable computing FPGA field programmable gate arrays. 2011-03-11T23:20:50-05:00 4 3/4 195 203 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39025 As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools for handling SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach for addressing system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC co-design framework: Gaspard2. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented works are based on model-driven engineering and the UML MARTE profile proposed by object management group, for modelling and analysis of real-time embedded systems. Our contributions thus relate to presenting a complete design flow to move from high level MARTE models to automatic code generation, for implementation of dynamically reconfigurable SoCs. Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation
Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatie, Eric Rutten, Samy Meftali, Jean-Luc Dekeyser
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 204 - 224
As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools for handling SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach for addressing system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC co-design framework: Gaspard2. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented works are based on model-driven engineering and the UML MARTE profile proposed by object management group, for modelling and analysis of real-time embedded systems. Our contributions thus relate to presenting a complete design flow to move from high level MARTE models to automatic code generation, for implementation of dynamically reconfigurable SoCs.

]]> 10.1504/IJES.2010.039025 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 204 - 224 Imran Rafiq Quadri Huafeng Yu Abdoulaye Gamatie Eric Rutten Samy Meftali Jean-Luc Dekeyser INRIA Lille Nord Europe – LIFL – USTL – CNRS, Park Plaza, 40 Avenue Halley, 56650 Villeneuve d'Ascq, France. ' IRISA/INRIA Rennes–Bretagne Atlantique, 263, Avenue du General Leclerc, 35042 Rennes, France. ' INRIA Lille Nord Europe – LIFL – USTL – CNRS, Park Plaza, 40 Avenue Halley, 56650 Villeneuve d'Ascq, France. ' INRIA Grenoble Rhone-Alpes, Inovallee, 655 Avenue de l'Europe, Montbonnot, 38344 Saint-Ismier cedex, France. ' INRIA Lille Nord Europe – LIFL – USTL – CNRS, Park Plaza, 40 Avenue Halley, 56650 Villeneuve d'Ascq, France. ' INRIA Lille Nord Europe – LIFL – USTL – CNRS, Park Plaza, 40 Avenue Halley, 56650 Villeneuve d'Ascq, France intensive signal processing UML MARTE model-driven engineering MDE systems-on-chip SoC co-design adaptive systems reconfigurability reconfigurable FPGA embedded systems modelling field programmable gate arrays. 2011-03-11T23:20:50-05:00 4 3/4 204 224 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39026 Run-time reconfiguration of field programmable devices can change their internal structure and behaviour in response to dynamic requests. Thus, reconfigurable systems with programmable fabrics can offer a cost effective solution to address the multi functionalities of today's applications. This paper recognises the cost benefits that such run-time adaptability can provide and proposes a novel reconfigurable architecture synthesis methodology to achieve a cost-effective reconfigurable system solution. The proposed architecture synthesis methodology converts a recognised dynamic environment into an assembled micro-level system. New design steps of the methodology identify a multi-task and multi-mode workload, determine an appropriate reconfiguration granularity and synthesise a workload-specific static architecture for a run-time reconfigurable system that enables on-chip assembly of pre-constructed components. The experimental results show the cost benefits of the proposed methodology which saves 73% of area and 29.8% of power compared to fixed design approach for implementing multiple visual processors. Architecture synthesis methodology for cost-effective run-time reconfigurable systems
Pil Woo Chun, Lev Kirischian
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 225 - 234
Run-time reconfiguration of field programmable devices can change their internal structure and behaviour in response to dynamic requests. Thus, reconfigurable systems with programmable fabrics can offer a cost effective solution to address the multi functionalities of today's applications. This paper recognises the cost benefits that such run-time adaptability can provide and proposes a novel reconfigurable architecture synthesis methodology to achieve a cost-effective reconfigurable system solution. The proposed architecture synthesis methodology converts a recognised dynamic environment into an assembled micro-level system. New design steps of the methodology identify a multi-task and multi-mode workload, determine an appropriate reconfiguration granularity and synthesise a workload-specific static architecture for a run-time reconfigurable system that enables on-chip assembly of pre-constructed components. The experimental results show the cost benefits of the proposed methodology which saves 73% of area and 29.8% of power compared to fixed design approach for implementing multiple visual processors.

]]> 10.1504/IJES.2010.039026 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 225 - 234 Pil Woo Chun Lev Kirischian Space Mission, MDA Corporation, 9445 Airport Rd., Brampton, Ontario, L6S 4J3, Canada. ' Electrical and Computer Engineering, Ryerson University, 350 Victoria St., Toronto, Ontario, M5B 2K3, Canada reconfigurable FPGA field programmable gate arrays architecture synthesis run-time reconfigurability stream applications multi-task systems embedded systems. 2011-03-11T23:20:50-05:00 4 3/4 225 234 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39027 Modern embedded systems execute a small set of applications or even a single one repeatedly. Specialising cache configurations to a particular application is well-known to have great benefits on performance and power. However, the fact that the behaviour of an application varies from phase to phase has been shown in recent years. Tuning cache configuration to fit a target application in different phases gives a further improvement in power consumption. This work presents a mechanism which determines the optimal configurations in different phases during an execution process. By applying corresponding cache configuration for each time interval of an execution process on L1 instruction cache, this work shows that on average 91.6% energy saving is obtained by comparing with average energy consumption of all four-way set-associative caches in search space. On average 5.29% power reduction is achieved by comparing with energy consumption of benchmarks with their respective global optimal cache configurations. Real-time reconfigurable cache for low-power embedded systems
Geng-Cyuan Jheng, Dyi-Rong Duh, Cheng-Nan Lai
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 235 - 247
Modern embedded systems execute a small set of applications or even a single one repeatedly. Specialising cache configurations to a particular application is well-known to have great benefits on performance and power. However, the fact that the behaviour of an application varies from phase to phase has been shown in recent years. Tuning cache configuration to fit a target application in different phases gives a further improvement in power consumption. This work presents a mechanism which determines the optimal configurations in different phases during an execution process. By applying corresponding cache configuration for each time interval of an execution process on L1 instruction cache, this work shows that on average 91.6% energy saving is obtained by comparing with average energy consumption of all four-way set-associative caches in search space. On average 5.29% power reduction is achieved by comparing with energy consumption of benchmarks with their respective global optimal cache configurations.

]]> 10.1504/IJES.2010.039027 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 235 - 247 Geng-Cyuan Jheng Dyi-Rong Duh Cheng-Nan Lai Department of Computer Science and Information Engineering, National Chi Nan University, Puli, Nantou Hsien 54561, Taiwan. ' Department of Computer Science and Information Engineering, National Chi Nan University, Puli, Nantou Hsien 54561, Taiwan. ' Department of Information Management, National Kaohsiung Marine University, Kaohsiung City 81143, Taiwan reconfigurable cache embedded systems power consumption benchmark real-time systems cache configurations. 2011-03-11T23:20:50-05:00 4 3/4 235 247 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39028 Chaotic filter bank schemes have been proposed in the research literature to allow for the efficient encryption of data for real-time embedded systems. Some security flaws have been found in the underlying approaches which makes such a scheme unsafe for application in real life scenarios. In this paper, we first present an improved scheme to alleviate the weaknesses of the chaotic filter bank scheme, and add enhanced security features, to form a modified chaotic filter bank (MCFB) scheme. Next, we present a reconfigurable hardware implementation of the MCFB scheme. Implementation on reconfigurable hardware speeds up the performance of MCFB scheme by mapping some of the multipliers in design to reconfigurable look-up tables, while removing many unnecessary multipliers. An optimised implementation on Xilinx Virtex-5 XC5VLX330 FPGA gave a speedup of 30% over non-optimised direct implementation. A clock frequency of 88 MHz was obtained. Reconfigurable hardware implementation of a modified chaotic filter bank scheme
A. Pande, J. Zambreno
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 248 - 258
Chaotic filter bank schemes have been proposed in the research literature to allow for the efficient encryption of data for real-time embedded systems. Some security flaws have been found in the underlying approaches which makes such a scheme unsafe for application in real life scenarios. In this paper, we first present an improved scheme to alleviate the weaknesses of the chaotic filter bank scheme, and add enhanced security features, to form a modified chaotic filter bank (MCFB) scheme. Next, we present a reconfigurable hardware implementation of the MCFB scheme. Implementation on reconfigurable hardware speeds up the performance of MCFB scheme by mapping some of the multipliers in design to reconfigurable look-up tables, while removing many unnecessary multipliers. An optimised implementation on Xilinx Virtex-5 XC5VLX330 FPGA gave a speedup of 30% over non-optimised direct implementation. A clock frequency of 88 MHz was obtained.

]]> 10.1504/IJES.2010.039028 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 248 - 258 A. Pande J. Zambreno Department of Electrical and Computer Engineering, Iowa State University, Ames, IA-50011, USA. ' Department of Electrical and Computer Engineering, Iowa State University, Ames, IA-50011, USA chaos theory encryption stream cipher reconfigurable FPGA chaotic filter banks real-time systems embedded systems field programmable gate arrays MCFB schemes. 2011-03-11T23:20:50-05:00 4 3/4 248 258 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39029 Multicore programming is more difficult than single-core programming, and developing applications on a complex multicore system without using an appropriate development environment is difficult, with the results being highly prone to error. A useful development environment for an embedded application design should contain programming models and development tools. The programming model provides a higher abstract level to control the communication and execution of multicore hardware, while the development tools help developers to debug applications and measure the performance of applications. In this paper, we propose a development environment for embedded multicore systems that includes a heterogeneous multicore simulation platform, customised compiler tools for a VLIW DSP, and a multicore programming model, streaming RPC. The experimental results demonstrate the high performance of the multicore simulation and compiler optimisations. The performance of compiled MiBench with O2 optimisation was 70% relative to no optimisation. Programming model and tools for embedded multicore systems
Chung-Wen Huang, Wen-Li Shih, Chung-Ju Wu, Jia-Jhe Li, Jenq Kuen Lee
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 259 - 269
Multicore programming is more difficult than single-core programming, and developing applications on a complex multicore system without using an appropriate development environment is difficult, with the results being highly prone to error. A useful development environment for an embedded application design should contain programming models and development tools. The programming model provides a higher abstract level to control the communication and execution of multicore hardware, while the development tools help developers to debug applications and measure the performance of applications. In this paper, we propose a development environment for embedded multicore systems that includes a heterogeneous multicore simulation platform, customised compiler tools for a VLIW DSP, and a multicore programming model, streaming RPC. The experimental results demonstrate the high performance of the multicore simulation and compiler optimisations. The performance of compiled MiBench with O2 optimisation was 70% relative to no optimisation.

]]> 10.1504/IJES.2010.039029 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 259 - 269 Chung-Wen Huang Wen-Li Shih Chung-Ju Wu Jia-Jhe Li Jenq Kuen Lee Department of Computer Science, National Tsing Hua University, No. 101, Section 2, Kuang-Fu Road, Hsinchu 30013, Taiwan. ' Department of Computer Science, National Tsing Hua University, No. 101, Section 2, Kuang-Fu Road, Hsinchu 30013, Taiwan. ' Department of Computer Science, National Tsing Hua University, No. 101, Section 2, Kuang-Fu Road, Hsinchu 30013, Taiwan. ' Department of Computer Science, National Tsing Hua University, No. 101, Section 2, Kuang-Fu Road, Hsinchu 30013, Taiwan. ' Department of Computer Science, National Tsing Hua University, No. 101, Section 2, Kuang-Fu Road, Hsinchu 30013, Taiwan multicore programming programming models VLIW compiler development tool embedded systems simulation. 2011-03-11T23:20:50-05:00 4 3/4 259 269 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39030 Hybrid multicore architecture consisting of tightly-integrated very long instruction word (VLIW) and superscalar processors can potentially take advantage of the heterogeneity of different cores to attain better performance. However, to implement or simulate a hybrid multicore processor is a challenging task due to the interactions of tightly integrated cores with different architectures/microarchitectures. In this paper, we design and implement two hybrid multicore architecture simulators for multi-program and multicore (MPMC) paradigm and single-program and multicore (SPMC) respectively. Based on these simulators, we provide preliminary results to evaluate the performance of the hybrid multicore processor for both multi-threaded and single-threaded programs. Design and implementation of hybrid multicore simulators
Jun Yan, Wei Zhang
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 270 - 275
Hybrid multicore architecture consisting of tightly-integrated very long instruction word (VLIW) and superscalar processors can potentially take advantage of the heterogeneity of different cores to attain better performance. However, to implement or simulate a hybrid multicore processor is a challenging task due to the interactions of tightly integrated cores with different architectures/microarchitectures. In this paper, we design and implement two hybrid multicore architecture simulators for multi-program and multicore (MPMC) paradigm and single-program and multicore (SPMC) respectively. Based on these simulators, we provide preliminary results to evaluate the performance of the hybrid multicore processor for both multi-threaded and single-threaded programs.

]]> 10.1504/IJES.2010.039030 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 270 - 275 Jun Yan Wei Zhang Mathworks Inc., 3 Apple Hill Drive, Natick, MA 01760-2098, USA. ' Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA 23284, USA multicore processors very long instruction word VLIW processors superscalar processors heterogeneous simulation. 2011-03-11T23:20:50-05:00 4 3/4 270 275 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39031 Dynamic reconfiguration provides attractive features such as hardware flexibility and adaptability. Unfortunately, the lack of programming tools to manage it has limited its use in current SoC. This paper presents a method to abstract dynamic reconfiguration management at design time. Dynamic hardware multiplexing is a generic principle based on a scheduler dedicated to the management of reconfigurable resources at run-time. Formal background, implementation, simulation results and validations are exposed to illustrate the contribution of this study. Run-time mapping for dynamic reconfiguration management in embedded systems
Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Nicolas Saint-Jean
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 276 - 291
Dynamic reconfiguration provides attractive features such as hardware flexibility and adaptability. Unfortunately, the lack of programming tools to manage it has limited its use in current SoC. This paper presents a method to abstract dynamic reconfiguration management at design time. Dynamic hardware multiplexing is a generic principle based on a scheduler dedicated to the management of reconfigurable resources at run-time. Formal background, implementation, simulation results and validations are exposed to illustrate the contribution of this study.

]]> 10.1504/IJES.2010.039031 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 276 - 291 Pascal Benoit Lionel Torres Gilles Sassatelli Michel Robert Nicolas Saint-Jean LIRMM, Montpellier Institute of Computer Science, Robotics and Microelectronics, University of Montpellier 2, CNRS, UMR 5506, 161, rue Ada, 34392 Montpellier Cedex 5, France. ' LIRMM, Montpellier Institute of Computer Science, Robotics and Microelectronics, University of Montpellier 2, CNRS, UMR 5506, 161, rue Ada, 34392 Montpellier Cedex 5, France. ' LIRMM, Montpellier Institute of Computer Science, Robotics and Microelectronics, University of Montpellier 2, CNRS, UMR 5506, 161, rue Ada, 34392 Montpellier Cedex 5, France. ' LIRMM, Montpellier Institute of Computer Science, Robotics and Microelectronics, University of Montpellier 2, CNRS, UMR 5506, 161, rue Ada, 34392 Montpellier Cedex 5, France. ' LIRMM, Montpellier Institute of Computer Science, Robotics and Microelectronics, University of Montpellier 2, CNRS, UMR 5506, 161, rue Ada, 34392 Montpellier Cedex 5, France reconfigurable computing run-time resource management self-adaptability task relocation task duplication task allocation scheduling hardware control software control embedded systems dynamic reconfiguration SoC systems on chip simulation. 2011-03-11T23:20:50-05:00 4 3/4 276 291 2011-03-11T23:20:50-05:00 http://www.inderscience.com/link.php?id=39032 This paper discusses the design and implementation of a new generation of digital stethoscopes capable of collecting and processing body sound without the need of a personnel computer and hardware interface. The cost of the proposed device is a fraction of that of the data acquisition system used with current digital stethoscopes to collect body sound in a digital format. The new design uses system-on-chip technology and hardware-software co-design to integrate all the functions needed by this application into a single field programmable gate array (FPGA). The new design strategy saves hardware, space, and power consumption. It also allows for signal processing and data interpretation in the same device. The body sound device has been implemented and tested. Its performance compares very favourably to that of existing PC-based digital stethoscope. Stand-alone portable digital body sound data acquisition device
Ali Alouani, Omar Elkeelany, Mohammed Abdallah
International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 292 - 297
This paper discusses the design and implementation of a new generation of digital stethoscopes capable of collecting and processing body sound without the need of a personnel computer and hardware interface. The cost of the proposed device is a fraction of that of the data acquisition system used with current digital stethoscopes to collect body sound in a digital format. The new design uses system-on-chip technology and hardware-software co-design to integrate all the functions needed by this application into a single field programmable gate array (FPGA). The new design strategy saves hardware, space, and power consumption. It also allows for signal processing and data interpretation in the same device. The body sound device has been implemented and tested. Its performance compares very favourably to that of existing PC-based digital stethoscope.

]]> 10.1504/IJES.2010.039032 International Journal of Embedded Systems, Vol. 4, No. 3/4 (2010) pp. 292 - 297 Ali Alouani Omar Elkeelany Mohammed Abdallah Department of Electrical and Computer Engineering, Tennessee Technological University, Cookeville, TN 38505, USA. ' Department of Electrical and Computer Engineering, Tennessee Technological University, Cookeville, TN 38505, USA. ' Department of Electrical and Computer Engineering, Tennessee Technological University, Cookeville, TN 38505, USA digital stethoscopes integrated data acquisition network-ready medical devices field programmable gate arrays FPGA flash memory body sound systems on chip SoC co-design signal processing. 2011-03-11T23:20:50-05:00 4 3/4 292 297 2011-03-11T23:20:50-05:00