Most recent issue published online in the International Journal of Circuits and Architecture Design.
International Journal of Circuits and Architecture Design
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International Journal of Circuits and Architecture Design
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© 2016 Inderscience Publishers Ltd
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International Journal of Circuits and Architecture Design
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http://www.inderscience.com/browse/index.php?journalID=414&year=2016&vol=2&issue=3/4
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Performance improvement in tree multiplier using full swing GDI logic based CLA adder
http://www.inderscience.com/link.php?id=89640
Designing multiplier with high speed low power and minimal layout structure is of prime importance. In this paper, we propose a new architecture of 8 × 8 Wallace tree multiplier by incorporating 4-2 compressor and full adder during the partial products reduction process. Also, the final carry propagate addition is performed by carry look ahead adder to reduce the delay. Further, the multiplier is implemented using full swing gate diffusion input (GDI) logic. This design is simulated using Cadence virtuoso at 45 nm technology model. The simulation results reveal that the proposed multiplier achieves 23% power reduction than the conventional tree multiplier. Also, a large amount of reduction in wiring head is attained for the proposed multiplier. Further, an analysis of circuit's performance variation with respect to process variations is done by Monte Carlo simulation. The results confirmed that proposed multiplier has more immune against process variation while comparing with existing designs.
Performance improvement in tree multiplier using full swing GDI logic based CLA adder
Shoba Mohan; Nakkeeran Rangaswamy
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 183 - 200
Designing multiplier with high speed low power and minimal layout structure is of prime importance. In this paper, we propose a new architecture of 8 × 8 Wallace tree multiplier by incorporating 4-2 compressor and full adder during the partial products reduction process. Also, the final carry propagate addition is performed by carry look ahead adder to reduce the delay. Further, the multiplier is implemented using full swing gate diffusion input (GDI) logic. This design is simulated using Cadence virtuoso at 45 nm technology model. The simulation results reveal that the proposed multiplier achieves 23% power reduction than the conventional tree multiplier. Also, a large amount of reduction in wiring head is attained for the proposed multiplier. Further, an analysis of circuit's performance variation with respect to process variations is done by Monte Carlo simulation. The results confirmed that proposed multiplier has more immune against process variation while comparing with existing designs.]]>
10.1504/IJCAD.2016.089640
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 183 - 200
Shoba Mohan
Nakkeeran Rangaswamy
Department of Electronics Engineering, School of Engineering and Technology, Pondicherry University, Puducherry-605014, India ' Department of Electronics Engineering, School of Engineering and Technology, Pondicherry University, Puducherry-605014, India
GDI logic
CLA adder
tree multiplier
power
digital circuit
2018-02-05T23:20:50-05:00
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200
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An efficient realisation of FIFO buffers for NoC routers using technology dependent optimisations targeting LUT based FPGAs
http://www.inderscience.com/link.php?id=89643
The communication between processing elements is facing challenges due to power, area and latency. The temporary flit storage blocks needed during communication contributes to the major power and area consumption in Network-on-Chip. Moreover, with modern FPGAs causing a rapid shift from prototype designing to low and medium volume productions, it becomes imperative to consider architectural optimisations that are specific to FPGA fabric only. This article attempts to provide novel optimised FIFO buffer realisation using technology dependent mapping strategies. This will help designers to adopt efficient design of NoC microarchitecture routers. The properties of proposed realisation are studied with a micro-architecture router for several packet flit rates given at an input port. The proposed realisation will help in the elimination of the presence of fixed inherent FIFO buffer instantiations as the proposed realisation gives us an idea to explore underlying FPGA fabric more efficiently for realisation of the FIFO than existing.
An efficient realisation of FIFO buffers for NoC routers using technology dependent optimisations targeting LUT based FPGAs
Liyaqat Nazir; Roohie Naaz Mir
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 201 - 232
The communication between processing elements is facing challenges due to power, area and latency. The temporary flit storage blocks needed during communication contributes to the major power and area consumption in Network-on-Chip. Moreover, with modern FPGAs causing a rapid shift from prototype designing to low and medium volume productions, it becomes imperative to consider architectural optimisations that are specific to FPGA fabric only. This article attempts to provide novel optimised FIFO buffer realisation using technology dependent mapping strategies. This will help designers to adopt efficient design of NoC microarchitecture routers. The properties of proposed realisation are studied with a micro-architecture router for several packet flit rates given at an input port. The proposed realisation will help in the elimination of the presence of fixed inherent FIFO buffer instantiations as the proposed realisation gives us an idea to explore underlying FPGA fabric more efficiently for realisation of the FIFO than existing.]]>
10.1504/IJCAD.2016.089643
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 201 - 232
Liyaqat Nazir
Roohie Naaz Mir
Department of CSE, National Institute of Technology Srinagar, India ' Department of CSE, National Institute of Technology Srinagar, India
depth
FIFO
network-on-chip
NoC
flits
traffic
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201
232
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Design of low power VCO based on single ended delay cells
http://www.inderscience.com/link.php?id=89647
This paper reports a hybrid ring VCO with low power consumption using single ended delay cells. A 3-stages VCO shows frequency variation from 2.049 GHz to 8.971 GHz with power consumption variation from 0.51 mW to 3.12 mW. In the 5-stages, VCO frequency varies from 1.153 GHz to 5.130 GHz with power consumption from 0.093 mW to 5.581 mW. Further, a 7-stages VCO provides frequency from 0.874 GHz to 3.678 GHz with power consumption from 0.138 mW to 8.041 mW. Tuning range of 125.63%, 126.59% and 123.19% has been achieved with the 3-stages, 5-stages and 7-stages VCO, respectively. Supply voltage has been varied from 1V to 3V. Phase noise of −83.1dBc/Hz at 1MHz, −90.6dBc/Hz at 1MHz and −90.8dBc/Hz at 1MHz have been reported for 3, 5 and 7-stages VCO, respectively. The figure of merit (FoM) of 156.4dBc/Hz, 160.8dBc/Hz and 156.5dBc/Hz has been observed for 3, 5 and 7-stages VCOs, respectively.
Design of low power VCO based on single ended delay cells
Dileep Dwivedi; Manoj Kumar
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 233 - 245
This paper reports a hybrid ring VCO with low power consumption using single ended delay cells. A 3-stages VCO shows frequency variation from 2.049 GHz to 8.971 GHz with power consumption variation from 0.51 mW to 3.12 mW. In the 5-stages, VCO frequency varies from 1.153 GHz to 5.130 GHz with power consumption from 0.093 mW to 5.581 mW. Further, a 7-stages VCO provides frequency from 0.874 GHz to 3.678 GHz with power consumption from 0.138 mW to 8.041 mW. Tuning range of 125.63%, 126.59% and 123.19% has been achieved with the 3-stages, 5-stages and 7-stages VCO, respectively. Supply voltage has been varied from 1V to 3V. Phase noise of −83.1dBc/Hz at 1MHz, −90.6dBc/Hz at 1MHz and −90.8dBc/Hz at 1MHz have been reported for 3, 5 and 7-stages VCO, respectively. The figure of merit (FoM) of 156.4dBc/Hz, 160.8dBc/Hz and 156.5dBc/Hz has been observed for 3, 5 and 7-stages VCOs, respectively.]]>
10.1504/IJCAD.2016.089647
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 233 - 245
Dileep Dwivedi
Manoj Kumar
University School of Information, Communication and Technology, Guru Gobind Singh Indraprastha University, New Delhi, India ' University School of Information, Communication and Technology, Guru Gobind Singh Indraprastha University, New Delhi, India
CMOS
inverter
low power
phase noise
power consumption
voltage controlled oscillator
VCO
2018-02-05T23:20:50-05:00
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Adder circuit design using quantum-dot cellular automata
http://www.inderscience.com/link.php?id=89672
In this discussion, we review quantum cellular automaton and base structures in QCA. We study full-adders having different number of gates performed until now. We also study QCA designer simulator with some design simulated using this software. Full-adders performed in QCA designer until now are of single and multi-layer types. In this research, we propose a one-bit one-layer full-adder with more efficiency in circuit performance. Through decreased number of cells, we managed to increase circuit performance velocity, and decrease space and expenses needed to produce it. The proposed circuit proved to have better efficiency. We conclude that the less number of cells we use in design of a full-adder, we obtain a full-adder with less delay, less space, less cost, more performance velocity, and on the whole, more efficiency.
Adder circuit design using quantum-dot cellular automata
Sahar Ghanbary; Mehrdad Maeen; Majid Haghparast
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 246 - 257
In this discussion, we review quantum cellular automaton and base structures in QCA. We study full-adders having different number of gates performed until now. We also study QCA designer simulator with some design simulated using this software. Full-adders performed in QCA designer until now are of single and multi-layer types. In this research, we propose a one-bit one-layer full-adder with more efficiency in circuit performance. Through decreased number of cells, we managed to increase circuit performance velocity, and decrease space and expenses needed to produce it. The proposed circuit proved to have better efficiency. We conclude that the less number of cells we use in design of a full-adder, we obtain a full-adder with less delay, less space, less cost, more performance velocity, and on the whole, more efficiency.]]>
10.1504/IJCAD.2016.089672
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 246 - 257
Sahar Ghanbary
Mehrdad Maeen
Majid Haghparast
Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran ' Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran ' Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran
quantum cellular automata
quantum points
full-adder design
QCA
2018-02-05T23:20:50-05:00
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Real-time implementation of various colour space models
http://www.inderscience.com/link.php?id=89654
The colour space translation plays a significant task in pre-processing stage of digital image processing. Colour conversion can improve the quality of images. The objective is to convert one colour space to another and the inverse of same. Various colour space conversions are used such as RGB ← → HSV, RGB ← → HSL, RGB ← → HSI, RGB ← → YUV and RGB ← → YCbCr. The conversion process can be done using colour space conversion algorithm. The colour space conversion is used in various applications such as commercial, multimedia, computer vision, visual tracking systems etc. The hardware realisation of colour space conversion models can be implemented by using Xilinx system generator on field programmable gate array spartan-6. Finally, the above colour space conversion models are implemented in real-time then tabulated in terms of percentage resources utilisation and power required. The recommended RGB ← → HSV colour space conversion utilises 21% of DSP48A1s chips and required 0.354 watts of power. By means of colour conversion, the efficiency and speed are increased.
Real-time implementation of various colour space models
Saravanan Govindasamy; Yamuna Govindarajan
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 258 - 271
The colour space translation plays a significant task in pre-processing stage of digital image processing. Colour conversion can improve the quality of images. The objective is to convert one colour space to another and the inverse of same. Various colour space conversions are used such as RGB ← → HSV, RGB ← → HSL, RGB ← → HSI, RGB ← → YUV and RGB ← → YCbCr. The conversion process can be done using colour space conversion algorithm. The colour space conversion is used in various applications such as commercial, multimedia, computer vision, visual tracking systems etc. The hardware realisation of colour space conversion models can be implemented by using Xilinx system generator on field programmable gate array spartan-6. Finally, the above colour space conversion models are implemented in real-time then tabulated in terms of percentage resources utilisation and power required. The recommended RGB ← → HSV colour space conversion utilises 21% of DSP48A1s chips and required 0.354 watts of power. By means of colour conversion, the efficiency and speed are increased.]]>
10.1504/IJCAD.2016.089654
International Journal of Circuits and Architecture Design, Vol. 2, No. 3/4 (2016) pp. 258 - 271
Saravanan Govindasamy
Yamuna Govindarajan
Department of Electrical and Electronics Engineering, Annamalai University, Annamalai Nagar-608001, Tamilnadu, India ' Department of Electrical and Electronics Engineering, Annamalai University, Annamalai Nagar-608001, Tamilnadu, India
colour space conversions
CSC
XSG
FPGA
Simulink
co-simulation
real-time image processing
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