Proceedings of the International Conference
I W S S I P   2005
12th INTERNATIONAL WORKSHOP ON SYSTEMS, SIGNALS & IMAGE PROCESSING

22 - 24 September 2005, Chalkida Greece
 
(from Chapter 1: Invited Addresses and Tutorials on Signals, Coding, Systems and Intelligent Techniques)

 Full Citation and Abstract

0 Title: Hardware implementation of 2D Discrete Wavelet Transform by using Non-separable Lifting Scheme
  Author(s): Safar Hatami, Shervin Sharifi, Mahmoud Kamarei, Hossein Ahmadi
  Address: Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran and University of British Columbia
s.hatami @ ece.ut.ac.ir, shervin @ cad.ece.ut.ac.ir, kamarei @ ut.ac.ir, ahmadi @ ece.ubc.ca
  Reference: SSIP-SP1, 2005  pp. 89 - 93
  Abstract/
Summary
In this paper, we propose an architecture that performs non-separable discrete wavelet transform (DWT) using a lifting scheme for (5,3) and (9,7) wavelets, the two major filters proposed in JPEG2000. It exploits advantages of lifting scheme such as low number of calculation and hardware similarity of forward and inverse DWT. The proposed architecture also inherits the characteristics of non-separable basis functions, such as compatibility with two-dimensional image scanning, and low latency and smaller hardware due to absence of transposition. The proposed hardware is a unified high throughput regular architecture, capable of executing (5,3) filter in lossless mode and (9,7) filter in lossy mode. It computes multilevel DWT while generating four outputs per cycle for (5,3) filter and two outputs per cycle for (9,7) filter. This architecture requires only one simple processor element and can achieve 100% utilization of hardware resources. The schedules of designed architecture have been generated manually. It has been simulated in system level and implemented in VHDL.
 
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